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Message-ID: <29056fd2b8ca260ebf7d3babb6c8cf2bf68a112a.camel@collabora.com>
Subject: Re: [PATCH] hantro: Fix RK3399 H.264 format advertising
From:   Nicolas Dufresne <nicolas.dufresne@collabora.com>
To:     Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>,
        linux-media@vger.kernel.org, linux-kernel@vger.kernel.org
Cc:     Hans Verkuil <hverkuil-cisco@xs4all.nl>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Benjamin Gaignard <benjamin.gaignard@collabora.com>
Date:   Wed, 29 Jun 2022 16:07:28 -0400
In-Reply-To: <20220629195624.45745-1-ezequiel@vanguardiasur.com.ar>
References: <20220629195624.45745-1-ezequiel@vanguardiasur.com.ar>
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Hi Ezequiel,

Le mercredi 29 juin 2022 =C3=A0 16:56 -0300, Ezequiel Garcia a =C3=A9crit=
=C2=A0:
> Commit 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2")
> enabled H.264 on some SoCs with VDPU2 cores. This had the side-effect
> of exposing H.264 coded format as supported on RK3399.
>=20
> Fix this and clarify how the codec is explicitly disabled on RK399 on

RK399 -> RK3399

> this driver.
>=20
> Fixes: 1f82f2df523cb ("media: hantro: Enable H.264 on Rockchip VDPU2")
> Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

Thanks for fixing this. The bogus format (without associated controls) is n=
ot
gone. With the right video node value:

  v4l2-ctl -D -dN --list-formats-out

Tested-By: Nicolas Dufresne <nicolas.dufresne@collabora.com>

> ---
>  .../staging/media/hantro/rockchip_vpu_hw.c    | 60 ++++++++++++++++---
>  1 file changed, 53 insertions(+), 7 deletions(-)
>=20
> diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/sta=
ging/media/hantro/rockchip_vpu_hw.c
> index 098486b9ec27..26e16b5a6a70 100644
> --- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
> +++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
> @@ -182,7 +182,7 @@ static const struct hantro_fmt rk3288_vpu_dec_fmts[] =
=3D {
>  	},
>  };
> =20
> -static const struct hantro_fmt rk3399_vpu_dec_fmts[] =3D {
> +static const struct hantro_fmt rockchip_vdpu2_dec_fmts[] =3D {
>  	{
>  		.fourcc =3D V4L2_PIX_FMT_NV12,
>  		.codec_mode =3D HANTRO_MODE_NONE,
> @@ -236,6 +236,47 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[]=
 =3D {
>  	},
>  };
> =20
> +static const struct hantro_fmt rk3399_vpu_dec_fmts[] =3D {
> +	{
> +		.fourcc =3D V4L2_PIX_FMT_NV12,
> +		.codec_mode =3D HANTRO_MODE_NONE,
> +		.frmsize =3D {
> +			.min_width =3D FMT_MIN_WIDTH,
> +			.max_width =3D FMT_FHD_WIDTH,
> +			.step_width =3D MB_DIM,
> +			.min_height =3D FMT_MIN_HEIGHT,
> +			.max_height =3D FMT_FHD_HEIGHT,
> +			.step_height =3D MB_DIM,
> +		},
> +	},
> +	{
> +		.fourcc =3D V4L2_PIX_FMT_MPEG2_SLICE,
> +		.codec_mode =3D HANTRO_MODE_MPEG2_DEC,
> +		.max_depth =3D 2,
> +		.frmsize =3D {
> +			.min_width =3D FMT_MIN_WIDTH,
> +			.max_width =3D FMT_FHD_WIDTH,
> +			.step_width =3D MB_DIM,
> +			.min_height =3D FMT_MIN_HEIGHT,
> +			.max_height =3D FMT_FHD_HEIGHT,
> +			.step_height =3D MB_DIM,
> +		},
> +	},
> +	{
> +		.fourcc =3D V4L2_PIX_FMT_VP8_FRAME,
> +		.codec_mode =3D HANTRO_MODE_VP8_DEC,
> +		.max_depth =3D 2,
> +		.frmsize =3D {
> +			.min_width =3D FMT_MIN_WIDTH,
> +			.max_width =3D FMT_UHD_WIDTH,
> +			.step_width =3D MB_DIM,
> +			.min_height =3D FMT_MIN_HEIGHT,
> +			.max_height =3D FMT_UHD_HEIGHT,
> +			.step_height =3D MB_DIM,
> +		},
> +	},
> +};
> +
>  static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
>  {
>  	struct hantro_dev *vpu =3D dev_id;
> @@ -548,8 +589,8 @@ const struct hantro_variant rk3288_vpu_variant =3D {
> =20
>  const struct hantro_variant rk3328_vpu_variant =3D {
>  	.dec_offset =3D 0x400,
> -	.dec_fmts =3D rk3399_vpu_dec_fmts,
> -	.num_dec_fmts =3D ARRAY_SIZE(rk3399_vpu_dec_fmts),
> +	.dec_fmts =3D rockchip_vdpu2_dec_fmts,
> +	.num_dec_fmts =3D ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
>  	.codec =3D HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
>  		 HANTRO_H264_DECODER,
>  	.codec_ops =3D rk3399_vpu_codec_ops,
> @@ -560,6 +601,11 @@ const struct hantro_variant rk3328_vpu_variant =3D {
>  	.num_clocks =3D ARRAY_SIZE(rockchip_vpu_clk_names),
>  };
> =20
> +/*
> + * H.264 decoding explicitly disabled in RK3399.
> + * This ensures userspace applications use the Rockchip VDEC core,
> + * which has better performance.
> + */
>  const struct hantro_variant rk3399_vpu_variant =3D {
>  	.enc_offset =3D 0x0,
>  	.enc_fmts =3D rockchip_vpu_enc_fmts,
> @@ -579,8 +625,8 @@ const struct hantro_variant rk3399_vpu_variant =3D {
> =20
>  const struct hantro_variant rk3568_vpu_variant =3D {
>  	.dec_offset =3D 0x400,
> -	.dec_fmts =3D rk3399_vpu_dec_fmts,
> -	.num_dec_fmts =3D ARRAY_SIZE(rk3399_vpu_dec_fmts),
> +	.dec_fmts =3D rockchip_vdpu2_dec_fmts,
> +	.num_dec_fmts =3D ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
>  	.codec =3D HANTRO_MPEG2_DECODER |
>  		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
>  	.codec_ops =3D rk3399_vpu_codec_ops,
> @@ -596,8 +642,8 @@ const struct hantro_variant px30_vpu_variant =3D {
>  	.enc_fmts =3D rockchip_vpu_enc_fmts,
>  	.num_enc_fmts =3D ARRAY_SIZE(rockchip_vpu_enc_fmts),
>  	.dec_offset =3D 0x400,
> -	.dec_fmts =3D rk3399_vpu_dec_fmts,
> -	.num_dec_fmts =3D ARRAY_SIZE(rk3399_vpu_dec_fmts),
> +	.dec_fmts =3D rockchip_vdpu2_dec_fmts,
> +	.num_dec_fmts =3D ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
>  	.codec =3D HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
>  		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
>  	.codec_ops =3D rk3399_vpu_codec_ops,

And code looks good (just found a small commit message typo).

Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>

regards,
Nicolas