Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <d0b68f0f-935e-3248-c60d-929705e4bc23@nvidia.com>
Date:   Thu, 30 Jun 2022 10:38:46 +0100
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101
 Thunderbird/91.9.1
Subject: Re: [PATCH v2 5/6] arm64: tegra: Enable native timers on Tegra194
Content-Language: en-US
To:     Kartik <kkartik@nvidia.com>, daniel.lezcano@linaro.org,
        tglx@linutronix.de, robh+dt@kernel.org, krzk+dt@kernel.org,
        thierry.reding@gmail.com, spujar@nvidia.com,
        akhilrajeev@nvidia.com, rgumasta@nvidia.com, pshete@nvidia.com,
        vidyas@nvidia.com, mperttunen@nvidia.com, mkumard@nvidia.com,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        linux-tegra@vger.kernel.org
References: <1656527344-28861-1-git-send-email-kkartik@nvidia.com>
 <1656527344-28861-6-git-send-email-kkartik@nvidia.com>
From:   Jon Hunter <jonathanh@nvidia.com>
In-Reply-To: <1656527344-28861-6-git-send-email-kkartik@nvidia.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?UmpKL2N0cFJhYnpycUU5OHVCOTlkTVZQOFNlckJzT2d0MjhmcmtHcytxcWQ2?=
 =?utf-8?B?eGwzTGt3R0RyS3ZDUjJJOHF2Nloyd0poczJDT2pvVjJqYmVrMU15WmpHZDRC?=
 =?utf-8?B?cTlpeDh5dmFLVUlCa25KUy9Ia215dTd4U3hUWktvODhCMnM0eVFOaXBDTlh1?=
 =?utf-8?B?TXptK1ZRU3dmc3IrQzRzQzE0Z2tXV1BrVXB6UjBxUUx3bkZJUnNKTVlxT0dC?=
 =?utf-8?B?ZWxtMTFPZFhNb3U2eGV4N3RmWXdFVVE4MWVxYXdIQVYwREdSUEFjVWNJL1Iy?=
 =?utf-8?B?Uk5mU2Vaa1FVQmxxRjNtT0JEdnlicUhwUExCdXpqams4ck5CU29NK25sdFJH?=
 =?utf-8?B?UUtETTBDNjVnc1BGb04zc25qSHgxRG9sMk8vOFltbUYwVjNYNkd4WUJ4Vkdk?=
 =?utf-8?B?eVBaREtHWDlRRjN6U1VUM2lKejNqWHJBelpEcFBoSVJHKzlqMzY1dllZSXdn?=
 =?utf-8?B?cXBOODdXeis4VzRrd1A3Ymd2NHhUbjNSZUZqTHBzTUlFaVg0WDJrenpRMmFE?=
 =?utf-8?B?NjdjVVJveWlEOXFLbC9aUDJTcE5aWlRhYURCa0szcnl6QUEyTDdrT3NtaVoz?=
 =?utf-8?B?dmMvcWs1ZFNmQW5penh2T21iNitNTElZV0tqZ1VGTUxDdDg5QzRvZ3dCNHVI?=
 =?utf-8?B?OTRMT3VINytkK0lPSXN4QnVRUGJxcmV5U28ydTBqMGJHSUpnTG5uUWFIMmYw?=
 =?utf-8?B?Tm1FUnVhVlZJejFZcFc0Nk5QcUtYMnlnQklIUmI5QjJSTG9WMGdnSzZRVVph?=
 =?utf-8?B?Z0NzMFo5dnk3eTVIemFkMkk1dkErbm9EbktBMHhNWVBFT2dITE5wZkUyamh6?=
 =?utf-8?B?Si9jc052anBBYjJiZk5wanZuV05PZWdGV3JQOGdwUWFTZHhVNnNBcURUTHQz?=
 =?utf-8?B?dkNFUmZMZU9TSzFWckVuN3kyNlNBdVhLdTY5TEV5dlFEazlRN0ZLYVVCbG90?=
 =?utf-8?B?ckF0MFIyRWJQd3lqV1FTUUZtWDBFb0xXU3R2a3hicHdxb2owL3ZUazZUbjZH?=
 =?utf-8?B?Nk1mbzR6dVA0b2paTXNYdmJVVnRVaDVqdDNDWEpoMTA3anNiTDNnRnlxRnQy?=
 =?utf-8?B?Vmpub3ZZaHlWWGR6V2x6TzhBT2hWWTdpZFpnZ3Vkb1hBa1BvOUQxYkxMMDI2?=
 =?utf-8?B?bk9mNytQWjJFRlJQdDB3QzdMYjMxQXlaNmtpYm9RWkVmNGxhOTZlZVJtMWZU?=
 =?utf-8?B?QUJTemRJL3dheE4vTU5GVkl3ZDRCNklrWWhZTzhMdlZNa24xZUYvcXhUTENK?=
 =?utf-8?B?ZHpjc0p1Tld6M2ppeCtXWGVOVEcweWxOb29MUlhnMjJYSENKNWF5d1FyVGQ2?=
 =?utf-8?B?aUpzSnU0cEYrZ1NUdEtmdHJMZzY1NzVjanprOEZjZDg0TEFEOTRNMWIrV0tU?=
 =?utf-8?B?VlNuMHZHVmVINzFENzc5SXpqRGE0YXhvNmVOSXBHUG90bElYS0xrT2k2UWU3?=
 =?utf-8?B?clZLWThMY2RZSlhNdDhtRVVad0VPNzV0SFI5eVJETTQ3K3Z4QVhUbnRtMWZW?=
 =?utf-8?B?UlAyOW9nVHJBOUx4eDhtd1hMQmhXRHVEVk9zVkdvWFJpSTgvWHRieExzdTYw?=
 =?utf-8?B?SE9PMFhCLzZrZHV0eCtaRTlCM2JJbGFiOU9vY1hieGVrL0hWemcrQ01Mdjdx?=
 =?utf-8?B?encyRmNkUmo2alFpT24xRmM4aTRnNkhMOVEyV3FVdDJsaFNvaWtXN0tMdXoz?=
 =?utf-8?B?S2tLdFFyeGxVS3VvMS8wcktwZTdxZ2RzWWJvUndtaEU3NHBncU90UVdCT0pp?=
 =?utf-8?B?TDBCeXpidk9VRXRPdUZLVkdyekdqRGI2NEh0VVNoN2xRM0VJcVlFTklHTk5v?=
 =?utf-8?B?QXNCajl3d1o5Z2xVMnBMYU40TVJtY0U2bHhObGo1SzRPajVVTDdLWUhVeGFn?=
 =?utf-8?B?RWN0M1NHUjRjclRMYXFHWFlZVXVDa0xjZ2MzK2psdzEzYUN0aUJnSE9iZlh5?=
 =?utf-8?B?WjhySEQ5bUNrUnJyVTJCQ1p4bmVlY0lDS2pGYlNzZFlFdzlhbnNJYTcrTUdw?=
 =?utf-8?B?OUdLMkd2enVNNnMxYXVGQ2tGT2xxSHo4bkN0Z0h6ZDVrSTNOVUx3bytLSFBv?=
 =?utf-8?B?cTMwV2lET2Z6ZFdqMDQ5eXQxYWh3RHRLQmRpME9XZmZBOEVaajRROEo2cVh4?=
 =?utf-8?B?Y24rcElYM0piSFZWNkhBclA5RksyUnVhdDFmbFl4c0M4SXZTREgzQzdHdnZS?=
 =?utf-8?B?UWc9PQ==?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 39668a20-150d-47b7-57de-08da5a7c58dd
X-MS-Exchange-CrossTenant-AuthSource: CO6PR12MB5444.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2022 09:38:54.1879
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: F46LKG7IEaYpPFSPJWVldmjuHz909FCez47ojR3Cj5jMu1CkRj36pz2kbc5nB9+9Ap/pJ2LihPu9XdV9f35RMA==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4706
X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
        DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,
        NICE_REPLY_A,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,
        SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no
        version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org


On 29/06/2022 19:29, Kartik wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The native timers IP block found on NVIDIA Tegra SoCs implements a
> watchdog timer that can be used to recover from system hangs. Add and
> enable the device tree node on Tegra194.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Kartik <kkartik@nvidia.com>
> ---
>   arch/arm64/boot/dts/nvidia/tegra194.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 9566c6388ed9..4b37aec69448 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -698,6 +698,22 @@
>   			};
>   		};
>   
> +		timer@3010000 {
> +			compatible = "nvidia,tegra186-timer";
> +			reg = <0x03010000 0x000e0000>;
> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "okay";
> +		};
> +
>   		uarta: serial@3100000 {
>   			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
>   			reg = <0x03100000 0x40>;


Reviewed-by: Jon Hunter <jonathanh@nvidia.com>

Thanks!
Jon

-- 
nvpublic