Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Received-SPF: Pass (protection.outlook.com: domain of amd.com designates
 165.204.84.17 as permitted sender) receiver=protection.outlook.com;
 client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C
Message-ID: <454ed57c-1482-b7dc-9434-1ca5888c8b66@amd.com>
Date:   Thu, 30 Jun 2022 12:59:09 +0200
MIME-Version: 1.0
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101
 Thunderbird/91.10.0
Subject: Re: [PATCH 1/4] dt-bindings: misc: tmr-manager: Add device-tree
 binding for TMR Manager
Content-Language: en-US
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        "Rao, Appana Durga Kedareswara" 
        <appana.durga.kedareswara.rao@amd.com>,
        "Appana Durga Kedareswara rao" <appana.durga.rao@xilinx.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "krzysztof.kozlowski+dt@linaro.org" 
        <krzysztof.kozlowski+dt@linaro.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "michal.simek@xilinx.com" <michal.simek@xilinx.com>,
        "derek.kiernan@xilinx.com" <derek.kiernan@xilinx.com>,
        "dragan.cvetic@xilinx.com" <dragan.cvetic@xilinx.com>,
        "arnd@arndb.de" <arnd@arndb.de>,
        "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>
CC:     "git (AMD-Xilinx)" <git@amd.com>, "git@xilinx.com" <git@xilinx.com>
References: <20220628054338.1631516-1-appana.durga.rao@xilinx.com>
 <20220628054338.1631516-2-appana.durga.rao@xilinx.com>
 <fc685f00-41e5-e64c-09b8-662b01a46f6c@linaro.org>
 <6f5a1b1e-b484-3a15-00be-2c1ddc09468e@amd.com>
 <e43bede7-2a0a-5114-e9ec-9e1449bf4e47@linaro.org>
 <a653cb16-4aa9-693a-ac32-cc7b1b999b92@amd.com>
 <dd709b5a-1cd8-0343-028a-5d134a9de81a@amd.com>
 <6fafbed8-9c6d-ae1b-c613-44982b681276@linaro.org>
From:   Michal Simek <michal.simek@amd.com>
In-Reply-To: <6fafbed8-9c6d-ae1b-c613-44982b681276@linaro.org>
Content-Type: text/plain; charset="UTF-8"; format=flowed
Content-Transfer-Encoding: 7bit
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2022 10:59:17.0029
 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 60951ae4-785a-47ae-7e3e-08da5a8793ba
X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com]
X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT018.eop-nam11.prod.protection.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Anonymous
X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5317
X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,
        RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE
        autolearn=ham autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org


On 6/30/22 12:07, Krzysztof Kozlowski wrote:
> On 29/06/2022 14:37, Rao, Appana Durga Kedareswara wrote:
>> Hi,
>>
>>
>> On 29/06/22 5:29 pm, Michal Simek wrote:
>>>
>>>
>>> On 6/29/22 13:45, Krzysztof Kozlowski wrote:
>>>> On 29/06/2022 13:23, Michal Simek wrote:
>>>>>
>>>>>
>>>>> On 6/29/22 12:07, Krzysztof Kozlowski wrote:
>>>>>> On 28/06/2022 07:43, Appana Durga Kedareswara rao wrote:
>>>>>>> This commit adds documentation for Triple Modular Redundancy(TMR)
>>>>>>> Manager
>>>>>>> IP. The Triple Modular Redundancy(TMR) Manager is responsible for
>>>>>>> handling
>>>>>>> the TMR subsystem state, including fault detection and error recovery
>>>>>>> provides soft error detection, correction and recovery features.
>>>>>>>
>>>>>>> Signed-off-by: Appana Durga Kedareswara rao
>>>>>>> <appana.durga.rao@xilinx.com>
>>>>>>> ---
>>>>>>>     .../bindings/misc/xlnx,tmr-manager.yaml       | 48
>>>>>>> +++++++++++++++++++
>>>>>>
>>>>>> This is not a misc device. Find appropriate subsystem for it. It's not
>>>>>> EDAC, right?
>>>>>
>>>>> We were thinking where to put it but it is not EDAC driver.
>>>>> If you have better suggestion for subsystem please let us know.
>>>>
>>>> I don't know what's the device about. The description does not help:
>>>>
>>>> "TMR Manager is responsible for TMR subsystem state..."
>>>
>>> ok. let's improve commit message in v2.
>>
>> Sure will improve the commit message in v2.
>>>
>>> TMR - triple module redundancy.
>>>
>>> You design the system with one CPU which is default microblaze
>>> configuration with interrupt controller, timer and other IPs.
>>>
>>> And then say I want to do it triple redundant with all that voting, etc.
>>> If you want to get all details you can take a look at this guide
>>>
>>> https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/tmr/v1_0/pg268-tmr.pdf
>>>
>>>
>>> In short TMR manager is servicing all that 3 cores and making sure that
>>> they are all running in sync. If not it has capability recover the
>>> system. It means cpu gets to break handler (it is the part of microblaze
>>> series) and it restarts all cpus.
>>>
>>> And TMR inject driver is module which is capable to inject error to
>>> internal memory to cause the exception to exercise that recovery code.
>>>
>>> Kedar: Feel free to correct me or add more details.
>>
>> Thanks Michal for the detailed explanation.
>>
>> The Triple Modular Redundancy(TMR) subsystem has three Microblaze
>> processor instances, If any one of the Microblaze processors goes to an
>> unknown state due to fault injection break handler will get called,
>> which in turn calls the tmr manager driver API to perform recovery.
>> like Michal said TMR inject driver is capable of inject error to
>> internal memory to cause fault in one the Microblaze processor
>>
>> @Krzysztof : please let me know if more information required about
>> this TMR subsystem will provide.
> 
> Some features sound like watchdog. 

watchdog needs to be keep alive which is not the case here. These systems are 
designed for safety or space applications and I am quite sure that there are 
going to be couple or regular watchdogs wired too.

> If it was ARM, I would suggest to put
> it under "soc". Is a term System-on-Chip applicable to Microblaze? 

I have never seen microblaze in connection to SOC. You can make SOC based on 
microblaze cpu (using hard cores) but in most cases microblaze as soft cpu is 
loaded to fpga or to programmable logic.

> Other
> option is to store it under microblaze (although for ARM and RISC-V this
> is actually discouraged in favor of soc).

Exactly. That was my main concern too that adding to microblaze is likely not 
the best location that's why we wanted to add it to different location.

Thanks,
Michal