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Message-ID: <c7d290bcca7bf5f78aee523c43df11b506eada89.camel@intel.com>
Subject: Re: [PATCH v7 037/102] KVM: x86/mmu: Track shadow MMIO value/mask
 on a per-VM basis
From:   Kai Huang <kai.huang@intel.com>
To:     isaku.yamahata@intel.com, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org
Cc:     isaku.yamahata@gmail.com, Paolo Bonzini <pbonzini@redhat.com>,
        Sean Christopherson <sean.j.christopherson@intel.com>
Date:   Thu, 30 Jun 2022 23:45:29 +1200
In-Reply-To: <242df8a7164b593d3702b9ba94889acd11f43cbb.1656366338.git.isaku.yamahata@intel.com>
References: <cover.1656366337.git.isaku.yamahata@intel.com>
         <242df8a7164b593d3702b9ba94889acd11f43cbb.1656366338.git.isaku.yamahata@intel.com>
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On Mon, 2022-06-27 at 14:53 -0700, isaku.yamahata@intel.com wrote:
> From: Sean Christopherson <sean.j.christopherson@intel.com>
>=20
> TDX will use a different shadow PTE entry value for MMIO from VMX.=C2=A0 =
Add
> members to kvm_arch and track value for MMIO per-VM instead of global
> variables.=C2=A0 By using the per-VM EPT entry value for MMIO, the existi=
ng VMX
> logic is kept working.
>=20
> In the case of VMX VM case, the EPT entry for MMIO is non-present PTE
> (present bit cleared) without backing guest physical address (on EPT
> violation, KVM searches backing guest memory and it finds there is no
> backing guest page.) or the value to trigger EPT misconfiguration.=C2=A0 =
Once
> MMIO is triggered on the EPT entry, the EPT entry is updated to trigger E=
PT
> misconfiguration for the future MMIO on the same GPA.=C2=A0 It allows KVM=
 to
> understand the memory access is for MMIO without searching backing guest
> pages.). And then KVM parses guest instruction to figure out
> address/value/width for MMIO.
>=20
> In the case of the guest TD, the guest memory is protected so that VMM
> can't parse guest instruction to understand the value and access width fo=
r
> MMIO.=C2=A0 Instead, VMM sets up (Shared) EPT to trigger #VE by clearing
> the VE-suppress bit.=C2=A0 When the guest TD issues MMIO, #VE is injected=
.=C2=A0 Guest VE
> handler converts MMIO access into MMIO hypercall to pass
> address/value/width for MMIO to VMM. (or directly paravirtualize MMIO int=
o
> hypercall.)=C2=A0 Then VMM can handle the MMIO hypercall without parsing =
guest
> instructions.

This is an infrastructural patch which enables per-VM MMIO caching.  Why no=
t
putting this patch first so you don't need to do below changes (which are
introduced by your previous patches)?

[...]

> =C2=A0
> -		if (!is_shadow_present_pte(spte) || is_mmio_spte(spte))
> +		if (!is_shadow_present_pte(spte) ||
> +		=C2=A0=C2=A0=C2=A0 is_mmio_spte(vcpu->kvm, spte))
> =C2=A0			break;
> =C2=A0
>=20

[...]

> @@ -1032,7 +1032,7 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, =
struct kvm_mmu_page *sp)
> =C2=A0		gfn_t gfn;
> =C2=A0
> =C2=A0		if (!is_shadow_present_pte(sp->spt[i]) &&
> -		=C2=A0=C2=A0=C2=A0 !is_mmio_spte(sp->spt[i]))
> +		=C2=A0=C2=A0=C2=A0 !is_mmio_spte(vcpu->kvm, sp->spt[i]))
> =C2=A0			continue;