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From:   Vladimir Oltean <vladimir.oltean@nxp.com>
To:     Colin Foster <colin.foster@in-advantage.com>
CC:     "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
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        Lee Jones <lee.jones@linaro.org>,
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        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
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        Lars Povlsen <lars.povlsen@microchip.com>,
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        Wolfram Sang <wsa@kernel.org>,
        Terry Bowman <terry.bowman@amd.com>,
        Andy Shevchenko <andy.shevchenko@gmail.com>
Subject: Re: [PATCH v11 net-next 8/9] dt-bindings: mfd: ocelot: add bindings
 for VSC7512
Thread-Topic: [PATCH v11 net-next 8/9] dt-bindings: mfd: ocelot: add bindings
 for VSC7512
Thread-Index: AQHYiseI5Ejf1g0+MkWBDpn74utZPa1n8gyA
Date:   Thu, 30 Jun 2022 13:17:54 +0000
Message-ID: <20220630131753.sjy4jjrdfqzfdk4n@skbuf>
References: <20220628081709.829811-1-colin.foster@in-advantage.com>
 <20220628081709.829811-9-colin.foster@in-advantage.com>
In-Reply-To: <20220628081709.829811-9-colin.foster@in-advantage.com>
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On Tue, Jun 28, 2022 at 01:17:08AM -0700, Colin Foster wrote:
> Add devicetree bindings for SPI-controlled Ocelot chips, specifically the
> VSC7512.
>=20
> Signed-off-by: Colin Foster <colin.foster@in-advantage.com>
> ---
>  .../devicetree/bindings/mfd/mscc,ocelot.yaml  | 160 ++++++++++++++++++
>  MAINTAINERS                                   |   1 +
>  2 files changed, 161 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mfd/mscc,ocelot.yam=
l
>=20
> diff --git a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml b/Doc=
umentation/devicetree/bindings/mfd/mscc,ocelot.yaml
> new file mode 100644
> index 000000000000..24fab9f5e319
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
> @@ -0,0 +1,160 @@
> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ocelot Externally-Controlled Ethernet Switch
> +
> +maintainers:
> +  - Colin Foster <colin.foster@in-advantage.com>
> +
> +description: |
> +  The Ocelot ethernet switch family contains chips that have an internal=
 CPU
> +  (VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switch=
es have
> +  the option to be controlled externally, which is the purpose of this d=
river.
> +
> +  The switch family is a multi-port networking switch that supports many
> +  interfaces. Additionally, the device can perform pin control, MDIO bus=
es, and
> +  external GPIO expanders.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - mscc,vsc7512-spi
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 1
> +
> +  spi-max-frequency:
> +    maxItems: 1
> +
> +patternProperties:
> +  "^pinctrl@[0-9a-f]+$":
> +    type: object
> +    $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
> +
> +  "^gpio@[0-9a-f]+$":
> +    type: object
> +    $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
> +    properties:
> +      compatible:
> +        enum:
> +          - mscc,ocelot-sgpio
> +
> +  "^mdio@[0-9a-f]+$":
> +    type: object
> +    $ref: /schemas/net/mscc,miim.yaml
> +    properties:
> +      compatible:
> +        enum:
> +          - mscc,ocelot-miim
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#address-cells'
> +  - '#size-cells'
> +  - spi-max-frequency
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    ocelot_clock: ocelot-clock {
> +          compatible =3D "fixed-clock";
> +          #clock-cells =3D <0>;
> +          clock-frequency =3D <125000000>;
> +      };
> +
> +    spi {
> +        #address-cells =3D <1>;
> +        #size-cells =3D <0>;
> +
> +        switch@0 {

I wonder if "switch" is the best name for the top-level node, since
there should also be another "switch" child node inside for the _actual_
DSA bindings, which this example is not showing (leading to further
confusion IMO).

Hmm, would "soc" be an exaggerated name? It's a SPI-controlled SoC after
all.

> +            compatible =3D "mscc,vsc7512";
> +            spi-max-frequency =3D <2500000>;
> +            reg =3D <0>;
> +            #address-cells =3D <1>;
> +            #size-cells =3D <1>;
> +
> +            mdio@7107009c {
> +                compatible =3D "mscc,ocelot-miim";
> +                #address-cells =3D <1>;
> +                #size-cells =3D <0>;
> +                reg =3D <0x7107009c 0x24>;
> +
> +                sw_phy0: ethernet-phy@0 {
> +                    reg =3D <0x0>;
> +                };
> +            };
> +
> +            mdio@710700c0 {
> +                compatible =3D "mscc,ocelot-miim";
> +                pinctrl-names =3D "default";
> +                pinctrl-0 =3D <&miim1_pins>;
> +                #address-cells =3D <1>;
> +                #size-cells =3D <0>;
> +                reg =3D <0x710700c0 0x24>;
> +
> +                sw_phy4: ethernet-phy@4 {
> +                    reg =3D <0x4>;
> +                };
> +            };
> +
> +            gpio: pinctrl@71070034 {
> +                compatible =3D "mscc,ocelot-pinctrl";
> +                gpio-controller;
> +                #gpio-cells =3D <2>;
> +                gpio-ranges =3D <&gpio 0 0 22>;
> +                reg =3D <0x71070034 0x6c>;
> +
> +                sgpio_pins: sgpio-pins {
> +                    pins =3D "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
> +                    function =3D "sg0";
> +                };
> +
> +                miim1_pins: miim1-pins {
> +                    pins =3D "GPIO_14", "GPIO_15";
> +                    function =3D "miim";
> +                };
> +            };
> +
> +            gpio@710700f8 {
> +                compatible =3D "mscc,ocelot-sgpio";
> +                #address-cells =3D <1>;
> +                #size-cells =3D <0>;
> +                bus-frequency =3D <12500000>;
> +                clocks =3D <&ocelot_clock>;
> +                microchip,sgpio-port-ranges =3D <0 15>;
> +                pinctrl-names =3D "default";
> +                pinctrl-0 =3D <&sgpio_pins>;
> +                reg =3D <0x710700f8 0x100>;
> +
> +                sgpio_in0: gpio@0 {
> +                    compatible =3D "microchip,sparx5-sgpio-bank";
> +                    reg =3D <0>;
> +                    gpio-controller;
> +                    #gpio-cells =3D <3>;
> +                    ngpios =3D <64>;
> +                };
> +
> +                sgpio_out1: gpio@1 {
> +                    compatible =3D "microchip,sparx5-sgpio-bank";
> +                    reg =3D <1>;
> +                    gpio-controller;
> +                    #gpio-cells =3D <3>;
> +                    ngpios =3D <64>;
> +                };
> +            };
> +        };
> +    };
> +
> +...
> +
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4d9ccec78f18..03eba7fd2141 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -14416,6 +14416,7 @@ F:	tools/testing/selftests/drivers/net/ocelot/*
>  OCELOT EXTERNAL SWITCH CONTROL
>  M:	Colin Foster <colin.foster@in-advantage.com>
>  S:	Supported
> +F:	Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
>  F:	include/linux/mfd/ocelot.h
> =20
>  OCXL (Open Coherent Accelerator Processor Interface OpenCAPI) DRIVER
> --=20
> 2.25.1
>=