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Date:   Thu, 30 Jun 2022 17:42:24 -0700
From:   "H. Peter Anvin" <hpa@zytor.com>
To:     Vasily Averin <vvs@openvz.org>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Andy Lutomirski <luto@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        x86@kernel.org
CC:     kernel@openvz.org, linux-kernel@vger.kernel.org,
        Konstantin Khorenko <khorenko@virtuozzo.com>,
        steve.sipes@comandsolutions.com
Subject: Re: [PATCH] x86/fault: ignore RSVD flag in error code if P flag is 0
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On June 29, 2022 10:58:36 PM PDT, Vasily Averin <vvs@openvz=2Eorg> wrote:
>Some older Intel CPUs have errata:
>"Not-Present Page Faults May Set the RSVD Flag in the Error Code
>
>Problem:
>An attempt to access a page that is not marked present causes a page
>fault=2E Such a page fault delivers an error code in which both the
>P flag (bit 0) and the RSVD flag (bit 3) are 0=2E Due to this erratum,
>not-present page faults may deliver an error code in which the P flag
>is 0 but the RSVD flag is 1=2E
>
>Implication:
>Software may erroneously infer that a page fault was due to a
>reserved-bit violation when it was actually due to an attempt
>to access a not-present page=2E
>
>Workaround: Page-fault handlers should ignore the RSVD flag in the error
>code if the P flag is 0=2E"
>
>This issues was observed on several nodes crashed with messages
>httpd: Corrupted page table at address 7f62d5b48e68
>PGD 80000002e92bf067 PUD 1c99c5067 PMD 195015067 PTE 7fffffffb78b680
>Bad pagetable: 000c [#1] SMP
>
>Let's follow the recommendation and will ignore the RSVD flag in the
>error code if the P flag is 0
>
>Link: https://lore=2Ekernel=2Eorg/all/aae9c7c6-989c-0261-470a-252537493b5=
3@openvz=2Eorg
>Signed-off-by: Vasily Averin <vvs@openvz=2Eorg>
>---
> arch/x86/mm/fault=2Ec | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
>diff --git a/arch/x86/mm/fault=2Ec b/arch/x86/mm/fault=2Ec
>index fe10c6d76bac=2E=2Effc6d6bd2a22 100644
>--- a/arch/x86/mm/fault=2Ec
>+++ b/arch/x86/mm/fault=2Ec
>@@ -1481,6 +1481,15 @@ handle_page_fault(struct pt_regs *regs, unsigned l=
ong error_code,
> 	if (unlikely(kmmio_fault(regs, address)))
> 		return;
>=20
>+	/*
>+	 * Some older Intel CPUs have errata
>+	 * "Not-Present Page Faults May Set the RSVD Flag in the Error Code"
>+	 * It is recommended to ignore the RSVD flag (bit 3) in the error code
>+	 * if the P flag (bit 0) is 0=2E
>+	 */
>+	if (unlikely((error_code & X86_PF_RSVD) && !(error_code & X86_PF_PROT))=
)
>+		error_code &=3D ~X86_PF_RSVD;
>+
> 	/* Was the fault on kernel-controlled part of the address space? */
> 	if (unlikely(fault_in_kernel_space(address))) {
> 		do_kern_addr_fault(regs, error_code, address);

Are there other bits we could/should mask=2Eout in the case P =3D 0? The o=
nly bits that should be able to appear are ones that are independent of the=
 PTE content=2E