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From:   Liu Ying <victor.liu@nxp.com>
To:     dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Cc:     andrzej.hajda@intel.com, narmstrong@baylibre.com,
        robert.foss@linaro.org, Laurent.pinchart@ideasonboard.com,
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        daniel@ffwll.ch, sam@ravnborg.org, marex@denx.de, linux-imx@nxp.com
Subject: [PATCH 0/3] drm/bridge: fsl-ldb: A few fixes
Date:   Fri,  1 Jul 2022 14:56:31 +0800
Message-Id: <20220701065634.4027537-1-victor.liu@nxp.com>
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Hi,

This series contains three fixes for the fsl-ldb bridge driver.

Patch 1/3 fixes mode clock rate validation.
Patch 2/3 fixes LVDS dual link mode.
Patch 3/3 fixes input data enable signal polarity.

Liu Ying (3):
  drm/bridge: fsl-ldb: Fix mode clock rate validation
  drm/bridge: fsl-ldb: Enable split mode for LVDS dual link
  drm/bridge: fsl-ldb: Drop DE signal polarity inversion

 drivers/gpu/drm/bridge/fsl-ldb.c | 21 ++-------------------
 1 file changed, 2 insertions(+), 19 deletions(-)

-- 
2.25.1