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Date:   Fri, 1 Jul 2022 09:35:48 +0200
From:   Markus Schneider-Pargmann <msp@baylibre.com>
To:     Linus Walleij <linus.walleij@linaro.org>
Cc:     Fabien Parent <fparent@baylibre.com>,
        Sean Wang <sean.wang@kernel.org>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken
 set/clr modes
Message-ID: <20220701073548.4za7fl2jodhpdaqe@blmsp>
References: <20220530123425.689459-1-fparent@baylibre.com>
 <CACRpkdYZJUWb4TBJiZVK4SNeA2Njn6341FuDjdYsn-0_yCeRKg@mail.gmail.com>
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Hi Linus,

On Wed, Jun 15, 2022 at 03:23:57PM +0200, Linus Walleij wrote:
> On Mon, May 30, 2022 at 2:35 PM Fabien Parent <fparent@baylibre.com> wrote:
> 
> > On MT8365, the SET/CLR of the mode is broken and some pin modes won't
> > be set correctly. Add a quirk for such SoCs, so that instead of using
> > the SET/CLR register use the main R/W register
> > to read/update/write the modes.
> >
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> 
> What is the state of this patch set? I see changes are requested by
> Angelo, are they being addressed?

I will probably pick up these patches and work on the comments, but I am
currently a bit busy on another project as well so it takes some time,
sorry.

Best,
Markus