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Date:   Fri, 1 Jul 2022 12:46:09 -0600
From:   Rob Herring <robh@kernel.org>
To:     Kartik <kkartik@nvidia.com>
Cc:     daniel.lezcano@linaro.org, tglx@linutronix.de, krzk+dt@kernel.org,
        thierry.reding@gmail.com, jonathanh@nvidia.com, spujar@nvidia.com,
        akhilrajeev@nvidia.com, rgumasta@nvidia.com, pshete@nvidia.com,
        vidyas@nvidia.com, mperttunen@nvidia.com, mkumard@nvidia.com,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        linux-tegra@vger.kernel.org
Subject: Re: [PATCH v2 1/6] dt-bindings: timer: Add Tegra186 & Tegra234 Timer
Message-ID: <20220701184609.GA1293870-robh@kernel.org>
References: <1656527344-28861-1-git-send-email-kkartik@nvidia.com>
 <1656527344-28861-2-git-send-email-kkartik@nvidia.com>
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On Wed, Jun 29, 2022 at 11:58:59PM +0530, Kartik wrote:
> The Tegra186 timer provides ten 29-bit timer counters and one 32-bit
> timestamp counter. The Tegra234 timer provides sixteen 29-bit timer
> counters and one 32-bit timestamp counter. Each NV timer selects its
> timing reference signal from the 1 MHz reference generated by USEC,
> TSC or either clk_m or OSC. Each TMR can be programmed to generate
> one-shot, periodic, or watchdog interrupts.
> 
> Signed-off-by: Kartik <kkartik@nvidia.com>
> ---
>  .../bindings/timer/nvidia,tegra186-timer.yaml | 111 ++++++++++++++++++
>  1 file changed, 111 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
> 
> diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
> new file mode 100644
> index 000000000000..5dc091532cd7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
> @@ -0,0 +1,111 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: NVIDIA Tegra186 timer
> +
> +maintainers:
> +  - Thierry Reding <treding@nvidia.com>
> +
> +description: >
> +  The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
> +  counter. Each NV timer selects its timing reference signal from the 1 MHz
> +  reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
> +  programmed to generate one-shot, periodic, or watchdog interrupts.
> +
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - const: nvidia,tegra186-timer
> +        description: >
> +          The Tegra186 timer provides ten 29-bit timer counters.
> +      - const: nvidia,tegra234-timer
> +        description: >
> +          The Tegra234 timer provides sixteen 29-bit timer counters.
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts: true
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: nvidia,tegra186-timer
> +    then:
> +      properties:
> +        interrupts:
> +          minItems: 1
> +          maxItems: 10
> +          description: >
> +            A list of 10 interrupts; one per each timer channels 0 through 9.

The schema says it is a list of 1 to 10 interrupts. Which is it. Surely 
the h/w is fixed. If so, drop 'minItems' and the first sentence.

> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: nvidia,tegra234-timer
> +    then:
> +      properties:
> +        interrupts:
> +          minItems: 1
> +          maxItems: 16
> +          description: >
> +            A list of 16 interrupts; one per each timer channels 0 through 15.

ditto

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    timer@3010000 {
> +        compatible = "nvidia,tegra186-timer";
> +        reg = <0x03010000 0x000e0000>;
> +        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +    };
> +
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    timer@2080000 {
> +        compatible = "nvidia,tegra234-timer";
> +        reg = <0x02080000 0x00121000>;
> +        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +    };
> -- 
> 2.17.1
> 
>