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Date:   Fri, 1 Jul 2022 14:54:44 -0600
From:   Rob Herring <robh@kernel.org>
To:     Shengjiu Wang <shengjiu.wang@nxp.com>
Cc:     Xiubo.Lee@gmail.com, nicoleotsuka@gmail.com,
        shengjiu.wang@gmail.com, linux-kernel@vger.kernel.org,
        lgirdwood@gmail.com, tiwai@suse.com, devicetree@vger.kernel.org,
        krzk+dt@kernel.org, perex@perex.cz, linuxppc-dev@lists.ozlabs.org,
        festevam@gmail.com, alsa-devel@alsa-project.org,
        broonie@kernel.org, robh+dt@kernel.org
Subject: Re: [PATCH v2 5/6] ASoC: dt-bindings: fsl_spdif: Add two PLL clock
 source
Message-ID: <20220701205444.GA1511232-robh@kernel.org>
References: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com>
 <1656667961-1799-6-git-send-email-shengjiu.wang@nxp.com>
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On Fri, 01 Jul 2022 17:32:40 +0800, Shengjiu Wang wrote:
> Add two PLL clock source, they are the parent clocks of root clock
> one is for 8kHz series rates, another one is for 11kHz series rates.
> They are optional clocks, if there are such clocks, then driver
> can switch between them for supporting more accurate rates.
> 
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> ---
>  Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>