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From:   Aleksander Jan Bajkowski <olek2@wp.pl>
To:     tsbogend@alpha.franken.de, olek2@wp.pl,
        martin.blumenstingl@googlemail.com, hauke@hauke-m.de,
        git@birger-koblitz.de, sander@svanheule.net,
        linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH] MIPS: smp-mt: enable all hardware interrupts on second VPE
Date:   Sat,  2 Jul 2022 21:07:05 +0200
Message-Id: <20220702190705.5319-1-olek2@wp.pl>
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This patch is needed to handle interrupts by the second VPE on
the Lantiq xRX200, xRX300 and xRX330 SoCs. In these chips, 32 ICU
interrupts are connected to each hardware line. The SoC supports
a total of 160 interrupts. Currently changing smp_affinity to the
second VPE hangs interrupts.

This problem affects multithreaded SoCs with a custom interrupt
controller. Chips with 1004Kc core and newer use the MIPS GIC.

Also CC'ed Birger Koblitz and Sander Vanheule. Both are working
on support for Realtek RTL930x chips with 34Kc core and Birger
has added a patch in OpenWRT that also enables all interrupt
lines. So it looks like this patch is useful for more SoCs.

Tested on lantiq xRX200 and xRX330.

Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
---
 arch/mips/kernel/smp-mt.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 5f04a0141068..f21cd0eb1fa7 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -113,8 +113,7 @@ static void vsmp_init_secondary(void)
 					 STATUSF_IP4 | STATUSF_IP5 |
 					 STATUSF_IP6 | STATUSF_IP7);
 	else
-		change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
-					 STATUSF_IP6 | STATUSF_IP7);
+		set_c0_status(ST0_IM);
 }
 
 static void vsmp_smp_finish(void)
-- 
2.30.2