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Message-ID: <3c9a032edd0fb9b9608ad3ca08d6e3cc38f21464.camel@svanheule.net>
Subject: Re: [PATCH] MIPS: smp-mt: enable all hardware interrupts on second
 VPE
From:   Sander Vanheule <sander@svanheule.net>
To:     Aleksander Jan Bajkowski <olek2@wp.pl>
Cc:     Marc Zyngier <maz@kernel.org>, tsbogend@alpha.franken.de,
        martin.blumenstingl@googlemail.com, hauke@hauke-m.de,
        git@birger-koblitz.de, linux-mips@vger.kernel.org,
        linux-kernel@vger.kernel.org
Date:   Sun, 03 Jul 2022 20:15:11 +0200
In-Reply-To: <20220702190705.5319-1-olek2@wp.pl>
References: <20220702190705.5319-1-olek2@wp.pl>
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Hi Aleksander,

Since this is IRQ related: +CC Marc Zyngier

On Sat, 2022-07-02 at 21:07 +0200, Aleksander Jan Bajkowski wrote:
> This patch is needed to handle interrupts by the second VPE on
> the Lantiq xRX200, xRX300 and xRX330 SoCs. In these chips, 32 ICU
> interrupts are connected to each hardware line. The SoC supports
> a total of 160 interrupts. Currently changing smp_affinity to the
> second VPE hangs interrupts.
>=20
> This problem affects multithreaded SoCs with a custom interrupt
> controller. Chips with 1004Kc core and newer use the MIPS GIC.
>=20
> Also CC'ed Birger Koblitz and Sander Vanheule. Both are working
> on support for Realtek RTL930x chips with 34Kc core and Birger
> has added a patch in OpenWRT that also enables all interrupt
> lines. So it looks like this patch is useful for more SoCs.
>=20
> Tested on lantiq xRX200 and xRX330.
>=20
> Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>

Thanks for bringing up this issue. Like you say OpenWrt carries a similar p=
atch, and I also carry a
patch on my tree to enable all CPU IRQ lines.

Indiscriminately enabling all IRQ lines doesn't sit quite right with me tho=
ugh, since I would expect
these to be enabled on-demand. I.e. when a peripheral requests an IRQ, or w=
hen an IRQ controller is
cascaded into one of the CPU's interrupt lines. If I understand correctly, =
the IRQ mask/unmask
functions in drivers/irqchip/irq-mips-cpu.c should do this.

I haven't been able to achieve this (automatic) behaviour until now, so I t=
hink I must be doing
something wrong when trying to cascade the SoC IRQ driver for the RTL839x/R=
TL930x chips into both
VPEs. It is currently not clear to me how this should be made functional wi=
thout a patch like this
one, so I hope we'll be able to clear that up now.

Best,
Sander

> ---
> =C2=A0arch/mips/kernel/smp-mt.c | 3 +--
> =C2=A01 file changed, 1 insertion(+), 2 deletions(-)
>=20
> diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
> index 5f04a0141068..f21cd0eb1fa7 100644
> --- a/arch/mips/kernel/smp-mt.c
> +++ b/arch/mips/kernel/smp-mt.c
> @@ -113,8 +113,7 @@ static void vsmp_init_secondary(void)
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 STATUSF_IP4 | STATUSF_IP5 |
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 STATUSF_IP6 | STATUSF_IP7);
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0else
> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 STATUSF_IP6 | STATUSF_IP7);
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0set_c0_status(ST0_IM);
> =C2=A0}
> =C2=A0
> =C2=A0static void vsmp_smp_finish(void)