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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y5-20020a170906470500b00722e5507498si489094ejq.75.2022.07.04.02.54.30; Mon, 04 Jul 2022 02:54:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@brainfault-org.20210112.gappssmtp.com header.s=20210112 header.b="G1fWW/mp"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233678AbiGDJgv (ORCPT + 99 others); Mon, 4 Jul 2022 05:36:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233808AbiGDJgo (ORCPT ); Mon, 4 Jul 2022 05:36:44 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E5C513B for ; Mon, 4 Jul 2022 02:36:42 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id cl1so12614422wrb.4 for ; Mon, 04 Jul 2022 02:36:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=q0TyLnReruI9Wm2732Ut83Y4mOFAKXfOkqxOXkTD/V8=; b=G1fWW/mpQ2bdGFNaIsSiqulbH86dbUIEM5HWmUU6f/ZgCaOYpV7OCKHesOvaS9YNmj AdoUT51LYOQeWxO1vgRknFPkdXOIRzDq9asQ6ILdueOBVe9dWBnLnmBn7PT0ilhPkr4W P1Qzki/cxPelPhc7+oB/wvESNGlC2E44VlUHGd/T0p2S93V/7425dJclQ78s+iuJRzac hRkYG82SWkWehe9nCNcbagVvjAOcOsMQb+U7fTN3GTJ+43Qg/OfpSY0lptPVgp2liJU7 CpSfGwAJkXHzzvOA06buA/Ljk7zlp+vV1Rfqoj6monK5miuZwezvA2bqHNPEp9aGRkXi HVAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=q0TyLnReruI9Wm2732Ut83Y4mOFAKXfOkqxOXkTD/V8=; b=4KKMgUVQ5TkrLpN9fBAca+zJ4f3/3VDVDxHjNxUi+pqe0R7jmY47TcpQPGQOMTSWcX 7hdATZrKwYhYqwOZEgBvSoTlYxa/CA8ysQTiqwBQFrc3CLo+cPD/xwggg3p0YYgLMntB GJfHUewWl9iCTPpropolgNFRFY9u4NiiA+hU6N/QQR859lNzFzvAb1YDbJCfuo2XwCTq nrmAuAHgfShLiaEWUss+KT9FYf+yUu7obaBtM+SAmPaieY30qNvigNeZDUKj842g8OVp 5BXmBlY5jo1qbHnpwwatYua5ZfA9/y3BdPkCTuFBx9aeFd2bAMkKoX47jdcE7i4WXZez Is6g== X-Gm-Message-State: AJIora+vI3fyoBjsVVFhc8WtpluE6VbrhpFsxRadDd4b9iEhjL1n5AI6 aSc+4ZkRL3FSuN4Fo50+IhyyFVtiUwVVgvvdvH4aMg== X-Received: by 2002:a5d:6b09:0:b0:21d:554f:b466 with SMTP id v9-20020a5d6b09000000b0021d554fb466mr11247084wrw.86.1656927400543; Mon, 04 Jul 2022 02:36:40 -0700 (PDT) MIME-Version: 1.0 References: <20220615104025.941382-1-apatel@ventanamicro.com> In-Reply-To: <20220615104025.941382-1-apatel@ventanamicro.com> From: Anup Patel Date: Mon, 4 Jul 2022 15:06:28 +0530 Message-ID: Subject: Re: [PATCH v2 0/3] Improve instruction and CSR emulation in KVM RISC-V To: Anup Patel Cc: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Alistair Francis , KVM General , "open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv)" , linux-riscv , "linux-kernel@vger.kernel.org List" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jun 15, 2022 at 4:10 PM Anup Patel wrote: > > Currently, the instruction emulation for MMIO traps and Virtual instruction > traps co-exist with general VCPU exit handling. The instruction and CSR > emulation will grow with upcoming SBI PMU, AIA, and Nested virtualization > in KVM RISC-V. In addition, we also need a mechanism to allow user-space > emulate certain CSRs under certain situation (example, host has AIA support > but user-space does not wants to use in-kernel AIA IMSIC and APLIC support). > > This series improves instruction and CSR emulation in KVM RISC-V to make > it extensible based on above. > > These patches can also be found in riscv_kvm_csr_v2 branch at: > https://github.com/avpatel/linux.git > > Changes since v1: > - Added a switch-case in PATCH3 to process MMIO, CSR, and SBI returned > from user-space > - Removed hard-coding in PATCH3 for determining type of CSR instruction > > Anup Patel (3): > RISC-V: KVM: Factor-out instruction emulation into separate sources > RISC-V: KVM: Add extensible system instruction emulation framework > RISC-V: KVM: Add extensible CSR emulation framework I have queued this series for 5.20 Thanks, Anup > > arch/riscv/include/asm/kvm_host.h | 16 +- > arch/riscv/include/asm/kvm_vcpu_insn.h | 48 ++ > arch/riscv/kvm/Makefile | 1 + > arch/riscv/kvm/vcpu.c | 34 +- > arch/riscv/kvm/vcpu_exit.c | 490 +---------------- > arch/riscv/kvm/{vcpu_exit.c => vcpu_insn.c} | 563 +++++++++++--------- > include/uapi/linux/kvm.h | 8 + > 7 files changed, 392 insertions(+), 768 deletions(-) > create mode 100644 arch/riscv/include/asm/kvm_vcpu_insn.h > copy arch/riscv/kvm/{vcpu_exit.c => vcpu_insn.c} (63%) > > -- > 2.34.1 >