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From:   Daire McNamara <daire.mcnamara@microchip.com>
To:     <conor@kernel.org>, <conor.dooley@microchip.com>
CC:     <aou@eecs.berkeley.edu>, <atishp@atishpatra.org>,
        <daire.mcnamara@microchip.com>, <devicetree@vger.kernel.org>,
        <ivan.griffin@microchip.com>, <krzysztof.kozlowski+dt@linaro.org>,
        <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
        <palmer@dabbelt.com>, <palmer@rivosinc.com>,
        <paul.walmsley@sifive.com>, <robh+dt@kernel.org>,
        <sudeep.holla@arm.com>
Subject: Re: [PATCH] riscv: dts: microchip: hook up the mpfs's l2cache
Date:   Tue, 5 Jul 2022 12:42:30 +0100
Message-ID: <20220705114229.2734205-1-daire.mcnamara@microchip.com>
In-Reply-To: <20220629200732.4039258-1-conor@kernel.org>
References: <20220629200732.4039258-1-conor@kernel.org>
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Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>

> From: Conor Dooley <conor.dooley@microchip.com>
> Date: Monday, 4 July 2022 at 10:04
> To: FPGA ESS Linux patches <FPGA-ESS-Linux-Patches@microchip.com>
> Cc: Conor Dooley - M52691 <Conor.Dooley@microchip.com>
> Subject: [PATCH] riscv: dts: microchip: hook up the mpfs' l2cache
> 
> The initial PolarFire SoC devicetree must have been forked off from
> the fu540 one prior to the addition of l2cache controller support being
> added there. When the controller node was added to mpfs.dtsi, it was
> not hooked up to the CPUs & thus sysfs reports an incorrect cache
> configuration. Hook it up.
> 
> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> index ed8739350587..2df555a57003 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> @@ -50,6 +50,7 @@ cpu1: cpu@1 {
>                          riscv,isa = "rv64imafdc";
>                          clocks = <&clkcfg CLK_CPU>;
>                          tlb-split;
> +                       next-level-cache = <&cctrllr>;
>                          status = "okay";
>  
>                          cpu1_intc: interrupt-controller {
> @@ -77,6 +78,7 @@ cpu2: cpu@2 {
>                          riscv,isa = "rv64imafdc";
>                          clocks = <&clkcfg CLK_CPU>;
>                          tlb-split;
> +                       next-level-cache = <&cctrllr>;
>                          status = "okay";
>  
>                          cpu2_intc: interrupt-controller {
> @@ -104,6 +106,7 @@ cpu3: cpu@3 {
>                          riscv,isa = "rv64imafdc";
>                          clocks = <&clkcfg CLK_CPU>;
>                          tlb-split;
> +                       next-level-cache = <&cctrllr>;
>                          status = "okay";
>  
>                          cpu3_intc: interrupt-controller {
> @@ -131,6 +134,7 @@ cpu4: cpu@4 {
>                          riscv,isa = "rv64imafdc";
>                          clocks = <&clkcfg CLK_CPU>;
>                          tlb-split;
> +                       next-level-cache = <&cctrllr>;
>                          status = "okay";
>                          cpu4_intc: interrupt-controller {
>                                  #interrupt-cells = <1>;
> -- 
> 2.36.1