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From:   Conor Dooley <mail@conchuod.ie>
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        daire.mcnamara@microchip.com, palmer@rivosinc.com,
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Cc:     Conor Dooley <conor.dooley@microchip.com>,
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        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv: dts: microchip: hook up the mpfs' l2cache
Date:   Tue,  5 Jul 2022 17:36:23 +0100
Message-Id: <165703891541.1175279.9783601760471076609.b4-ty@microchip.com>
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From: Conor Dooley <conor.dooley@microchip.com>

On Wed, 29 Jun 2022 21:07:33 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> The initial PolarFire SoC devicetree must have been forked off from
> the fu540 one prior to the addition of l2cache controller support being
> added there. When the controller node was added to mpfs.dtsi, it was
> not hooked up to the CPUs & thus sysfs reports an incorrect cache
> configuration. Hook it up.
> 
> [...]

Applied to dt-fixes, thanks!

[1/1] riscv: dts: microchip: hook up the mpfs' l2cache
      https://git.kernel.org/conor/c/efa310ba0071

Thanks,
Conor.