Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
MIME-Version: 1.0
References: <20220705163136.2278662-1-vincent.knecht@mailoo.org> <20220705163136.2278662-6-vincent.knecht@mailoo.org>
In-Reply-To: <20220705163136.2278662-6-vincent.knecht@mailoo.org>
From:   Andy Shevchenko <andy.shevchenko@gmail.com>
Date:   Tue, 5 Jul 2022 20:51:52 +0200
Message-ID: <CAHp75VexCGKRVovaMhfzonFkju6vh_TR6_A3vLtZVox3AhAvYg@mail.gmail.com>
Subject: Re: [PATCH v3 5/6] leds: is31fl319x: Move chipset-specific values in
 chipdef struct
To:     Vincent Knecht <vincent.knecht@mailoo.org>
Cc:     Pavel Machek <pavel@ucw.cz>, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Linux LED Subsystem <linux-leds@vger.kernel.org>,
        devicetree <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org,
        "H. Nikolaus Schaller" <hns@goldelico.com>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

On Tue, Jul 5, 2022 at 6:33 PM Vincent Knecht <vincent.knecht@mailoo.org> wrote:
>
> Allow setting chips' specifics in chipdef struct by adding fields for:
> - the reset register address
> - a pointer to a regmap_config struct
> - a pointer to a brightness_set function
> - current default, min and max values
> - a boolean to distinguish 319{0,1,3} and 319{6,9} chips
> and use those fields in places where distinction has to be made.
>
> The fields for 319{0,1,3} still point to 319{6,9} values.
> No functional change.

...

> +static bool is31fl319x_readable_reg(struct device *dev, unsigned int reg)
> +{ /* we have no readable registers */

Non-standard place for comments.

> +       return false;
> +}

...

> +static const struct reg_default is31fl3196_reg_defaults[] = {
> +       { IS31FL3196_CONFIG1, 0x00},
> +       { IS31FL3196_CONFIG2, 0x00},
> +       { IS31FL3196_PWM(0), 0x00},
> +       { IS31FL3196_PWM(1), 0x00},
> +       { IS31FL3196_PWM(2), 0x00},
> +       { IS31FL3196_PWM(3), 0x00},
> +       { IS31FL3196_PWM(4), 0x00},
> +       { IS31FL3196_PWM(5), 0x00},
> +       { IS31FL3196_PWM(6), 0x00},
> +       { IS31FL3196_PWM(7), 0x00},
> +       { IS31FL3196_PWM(8), 0x00},

Missed space before }.

>  };

-- 
With Best Regards,
Andy Shevchenko