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From:   =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
To:     Michael Ellerman <mpe@ellerman.id.au>,
        Benjamin Herrenschmidt <benh@kernel.crashing.org>,
        Paul Mackerras <paulus@samba.org>,
        Christophe Leroy <christophe.leroy@csgroup.eu>,
        =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>,
        Nick Child <nick.child@ibm.com>,
        Bjorn Helgaas <helgaas@kernel.org>
Cc:     linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: [PATCH 0/5] powerpc/pci: Cleanup unused code and enable 256 PCI buses
Date:   Wed,  6 Jul 2022 12:43:03 +0200
Message-Id: <20220706104308.5390-1-pali@kernel.org>
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This patch series cleanup unused code by eliminating it at compile time
and then enable usage of all 256 PCI buses per every PCI domain as
currently PCI bus numbers have to be unique across all PCI domains.
So first bus number of each PCI domain would be zero and not the bus
number of the previous domain plus one. As such bus assignment changes
BDF address of every PCI device on multi-domain system, this new
"feature" is configurable by config option to prevent regressions.

Tested on Freescale P2020 board. Before this patch lspci reports:

8000:00:00.0 PCI bridge: Freescale Semiconductor Inc P2020E (rev 21)
8000:01:00.0 USB controller: Texas Instruments TUSB73x0 SuperSpeed USB 3.0 xHCI Host Controller (rev 02)
9000:02:00.0 PCI bridge: Freescale Semiconductor Inc P2020E (rev 21)
9000:03:00.0 Network controller: Qualcomm Atheros AR93xx Wireless Network Adapter (rev 01)
a000:04:00.0 PCI bridge: Freescale Semiconductor Inc P2020E (rev 21)
a000:05:00.0 Network controller: Qualcomm Atheros QCA986x/988x 802.11ac Wireless Network Adapter

With these patches and enabled config option it reports:

8000:00:00.0 PCI bridge: Freescale Semiconductor Inc P2020E (rev 21)
8000:01:00.0 USB controller: Texas Instruments TUSB73x0 SuperSpeed USB 3.0 xHCI Host Controller (rev 02)
9000:00:00.0 PCI bridge: Freescale Semiconductor Inc P2020E (rev 21)
9000:01:00.0 Network controller: Qualcomm Atheros AR93xx Wireless Network Adapter (rev 01)
a000:00:00.0 PCI bridge: Freescale Semiconductor Inc P2020E (rev 21)
a000:01:00.0 Network controller: Qualcomm Atheros QCA986x/988x 802.11ac Wireless Network Adapter

Now every PCIe Root Port is on bus zero and theoretically with enough
multiport PCIe switches connected to every PCIe Root Port, it should be
possible to have 256 PCI buses on every PCIe controller (as each is in
own PCI domain) and therefore connect more PCIe cards as without these
patches.

Pali Rohár (5):
  powerpc/pci: Hide pci_device_from_OF_node() for non-powermac code
  powerpc/pci: Make pcibios_make_OF_bus_map() static
  powerpc/pci: Hide pci_create_OF_bus_map() for non-chrp code
  powerpc/pci: Disable filling pci-OF-bus-map for non-chrp/powermac
  powerpc/pci: Add config option for using all 256 PCI buses

 arch/powerpc/Kconfig                  | 11 +++++++++++
 arch/powerpc/include/asm/pci-bridge.h |  4 ++++
 arch/powerpc/kernel/pci_32.c          | 27 +++++++++++++++++++++------
 arch/powerpc/kernel/pci_64.c          |  2 ++
 4 files changed, 38 insertions(+), 6 deletions(-)

-- 
2.20.1