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Date:   Wed, 6 Jul 2022 22:21:39 +0530
From:   Vinod Koul <vkoul@kernel.org>
To:     Wangseok Lee <wangseok.lee@samsung.com>
Cc:     "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "krzk+dt@kernel.org" <krzk+dt@kernel.org>,
        "kishon@ti.com" <kishon@ti.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "jesper.nilsson@axis.com" <jesper.nilsson@axis.com>,
        "lars.persson@axis.com" <lars.persson@axis.com>,
        "bhelgaas@google.com" <bhelgaas@google.com>,
        "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
        "kw@linux.com" <kw@linux.com>,
        "linux-arm-kernel@axis.com" <linux-arm-kernel@axis.com>,
        "kernel@axis.com" <kernel@axis.com>,
        Moon-Ki Jun <moonki.jun@samsung.com>,
        Sang Min Kim <hypmean.kim@samsung.com>,
        Dongjin Yang <dj76.yang@samsung.com>,
        Yeeun Kim <yeeun119.kim@samsung.com>
Subject: Re: [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver
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On 06-07-22, 17:10, Wangseok Lee wrote:
> On?05-07-22,?15:30,?Vinod Koul?wrote:
> > On?14-06-22,?10:34,?Wangseok?Lee?wrote:
> >>?Add?support?Axis,?ARTPEC-8?SoC.
> >>?ARTPEC-8?is?the?SoC?platform?of?Axis?Communications.
> >>?This?is?based?on?arm64?and?support?GEN4?&?2lane.
> >>?This?driver?provides?PHY?interface?for?ARTPEC-8?SoC?PCIe?controller,
> >>?based?on?Samsung?PCIe?PHY?IP.
> >> 
> >> Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com>
> >> Signed-off-by: Jaeho Cho <jaeho79.cho@samsung.com>
> >> ---
> >> v2->v3 :
> >> -remove unnecessary indentation
> >> -redefine local struct to statis const
> >> -add static const to struct that requires static const definition
> >> -remove wrappers on writel and readl
> >> 
> >> v1->v2 :
> >> -change folder name of phy driver to axis from artpec
> >> ---
> >>  drivers/phy/Kconfig                 |   1 +
> >>  drivers/phy/Makefile                |   1 +
> >>  drivers/phy/axis/Kconfig            |   9 +
> >>  drivers/phy/axis/Makefile           |   2 +
> >>  drivers/phy/axis/phy-artpec8-pcie.c | 776 ++++++++++++++++++++++++++++++++++++
> >>  5 files changed, 789 insertions(+)
> >>  create mode 100644 drivers/phy/axis/Kconfig
> >>  create mode 100644 drivers/phy/axis/Makefile
> >>  create mode 100644 drivers/phy/axis/phy-artpec8-pcie.c
> >> 
> >> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> >> index 300b0f2..92b8232 100644
> >> --- a/drivers/phy/Kconfig
> >> +++ b/drivers/phy/Kconfig
> >> @@ -73,6 +73,7 @@ config PHY_CAN_TRANSCEIVER
> >>??
> >>??source?"drivers/phy/allwinner/Kconfig"
> >>??source?"drivers/phy/amlogic/Kconfig"
> >>?+source?"drivers/phy/axis/Kconfig"
> >>??source?"drivers/phy/broadcom/Kconfig"
> >>??source?"drivers/phy/cadence/Kconfig"
> >>??source?"drivers/phy/freescale/Kconfig"
> >>?diff?--git?a/drivers/phy/Makefile?b/drivers/phy/Makefile
> >>?index?01e9eff..808c055e?100644
> >>?---?a/drivers/phy/Makefile
> >>?+++?b/drivers/phy/Makefile
> >>?@@?-12,6?+12,7?@@?obj-$(CONFIG_PHY_PISTACHIO_USB)????????????????+=?phy-pistachio-usb.o
> >>??obj-$(CONFIG_USB_LGM_PHY)????????????????+=?phy-lgm-usb.o
> >>??obj-y????????????????????????????????????????+=?allwinner/????????\
> >>?????????????????????????????????????????????amlogic/????????\
> >>?+???????????????????????????????????????????axis/????????????????\
> >>?????????????????????????????????????????????broadcom/????????\
> >>?????????????????????????????????????????????cadence/????????\
> >>?????????????????????????????????????????????freescale/????????\
> >>?diff?--git?a/drivers/phy/axis/Kconfig?b/drivers/phy/axis/Kconfig
> >>?new?file?mode?100644
> >>?index?0000000..7198b93
> >>?---?/dev/null
> >>?+++?b/drivers/phy/axis/Kconfig
> >>?@@?-0,0?+1,9?@@
> >>?+config?PHY_ARTPEC8_PCIE
> >>?+????????bool?"ARTPEC-8?PCIe?PHY?driver"
> >>?+????????depends?on?OF?&&?(ARCH_ARTPEC8?||?COMPILE_TEST)
> >>?+????????select?GENERIC_PHY
> >>?+????????help
> >>?+??????????Enable?PCIe?PHY?support?for?ARTPEC-8?SoC.
> >>?+??????????This?driver?provides?PHY?interface?for?ARTPEC-8?SoC
> >>?+??????????PCIe?controller.
> >>?+??????????This?is?based?on?Samsung?PCIe?PHY?IP.
> > 
> > How?different?is?it?from?SS?IP?and?why?should?it?not?be?under
> > phy/samsung/?then?
> > 
> 
> SoC platform is completely different from exynos platform and different 
> from exynos PCIe PHY. So the overall sysreg configuration is different
> and register map is also different. The reset method and type of PHY for
> initialization are different. This is not a driver that supports Samsung
> SoC platform, but this PHY driver that supports only Axis, Artpec-8
> platforms, so it is not added to phy/samsung.

SoC is a moot point. If the IP block is same then we should try to reuse
the existing phy driver, modifications to current driver to support your
changes should be fine...

Is that feasible?

-- 
~Vinod