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In-Reply-To: <69e3fec3-bd49-8877-f1f8-453b09b8c940@quicinc.com>
From:   Doug Anderson <dianders@chromium.org>
Date:   Wed, 6 Jul 2022 11:21:36 -0700
Message-ID: <CAD=FV=VhA=iGnip_DOdNOZn_mjqgC=37o4tWFQXNpTAqf=09sA@mail.gmail.com>
Subject: Re: [V2] tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which
 otherwise could return a sub-optimal clock rate.
To:     Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
Cc:     "Vijaya Krishna Nivarthi (Temp)" <vnivarth@qti.qualcomm.com>,
        Andy Gross <agross@kernel.org>,
        "bjorn.andersson@linaro.org" <bjorn.andersson@linaro.org>,
        Konrad Dybcio <konrad.dybcio@somainline.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Jiri Slaby <jirislaby@kernel.org>,
        linux-arm-msm <linux-arm-msm@vger.kernel.org>,
        "linux-serial@vger.kernel.org" <linux-serial@vger.kernel.org>,
        LKML <linux-kernel@vger.kernel.org>,
        "Mukesh Savaliya (QUIC)" <quic_msavaliy@quicinc.com>,
        Matthias Kaehlcke <mka@chromium.org>,
        Stephen Boyd <swboyd@chromium.org>
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Hi,

On Wed, Jul 6, 2022 at 10:44 AM Vijaya Krishna Nivarthi
<quic_vnivarth@quicinc.com> wrote:
>
> Hi,
>
>
> On 7/6/2022 8:56 PM, Doug Anderson wrote:
> > Hi,
> >
> > On Mon, Jul 4, 2022 at 11:57 AM Vijaya Krishna Nivarthi (Temp)
> > <vnivarth@qti.qualcomm.com> wrote:
> >> Hi,
> >>
> >>
> >>> -----Original Message-----
> >>> From: Doug Anderson <dianders@chromium.org>
> >>> Sent: Friday, July 1, 2022 8:38 PM
> >>> To: Vijaya Krishna Nivarthi (Temp) (QUIC) <quic_vnivarth@quicinc.com>
> >>> Cc: Andy Gross <agross@kernel.org>; bjorn.andersson@linaro.org; Konra=
d
> >>> Dybcio <konrad.dybcio@somainline.org>; Greg Kroah-Hartman
> >>> <gregkh@linuxfoundation.org>; Jiri Slaby <jirislaby@kernel.org>; linu=
x-arm-
> >>> msm <linux-arm-msm@vger.kernel.org>; linux-serial@vger.kernel.org; LK=
ML
> >>> <linux-kernel@vger.kernel.org>; Mukesh Savaliya (QUIC)
> >>> <quic_msavaliy@quicinc.com>; Matthias Kaehlcke <mka@chromium.org>;
> >>> Stephen Boyd <swboyd@chromium.org>
> >>> Subject: Re: [V2] tty: serial: qcom-geni-serial: Fix get_clk_div_rate=
() which
> >>> otherwise could return a sub-optimal clock rate.
> >>>
> >>> WARNING: This email originated from outside of Qualcomm. Please be wa=
ry
> >>> of any links or attachments, and do not enable macros.
> >>>
> >>> Hi,
> >>>
> >>> On Fri, Jul 1, 2022 at 4:04 AM Vijaya Krishna Nivarthi (Temp) (QUIC)
> >>> <quic_vnivarth@quicinc.com> wrote:
> >>>> Hi,
> >>>>
> >>>>
> >>>>> -----Original Message-----
> >>>>> From: Doug Anderson <dianders@chromium.org>
> >>>>> Sent: Thursday, June 30, 2022 4:45 AM
> >>>>> To: Vijaya Krishna Nivarthi (Temp) (QUIC)
> >>>>> <quic_vnivarth@quicinc.com>
> >>>>> Cc: Andy Gross <agross@kernel.org>; bjorn.andersson@linaro.org;
> >>>>> Konrad Dybcio <konrad.dybcio@somainline.org>; Greg Kroah-Hartman
> >>>>> <gregkh@linuxfoundation.org>; Jiri Slaby <jirislaby@kernel.org>;
> >>>>> linux-arm- msm <linux-arm-msm@vger.kernel.org>;
> >>>>> linux-serial@vger.kernel.org; LKML <linux-kernel@vger.kernel.org>;
> >>>>> Mukesh Savaliya (QUIC) <quic_msavaliy@quicinc.com>; Matthias
> >>>>> Kaehlcke <mka@chromium.org>; Stephen Boyd
> >>> <swboyd@chromium.org>
> >>>>> Subject: Re: [V2] tty: serial: qcom-geni-serial: Fix
> >>>>> get_clk_div_rate() which otherwise could return a sub-optimal clock=
 rate.
> >>>>>
> >>>>>
> >>>>>
> >>>>>> +                               /* Save the first (lowest freq) wi=
thin tolerance */
> >>>>>> +                               ser_clk =3D freq;
> >>>>>> +                               *clk_div =3D new_div;
> >>>>>> +                               /* no more search for exact match =
required in 2nd run
> >>> */
> >>>>>> +                               if (!exact_match)
> >>>>>> +                                       break;
> >>>>>> +                       }
> >>>>>> +               }
> >>>>>>
> >>>>>> -               prev =3D freq;
> >>>>>> +               div =3D freq / desired_clk + 1;
> >>>>> Can't you infinite loop now?
> >>>>>
> >>>>> Start with:
> >>>>>
> >>>>> desired_clk =3D 10000
> >>>>> div =3D 1
> >>>>> percent_tol =3D 2
> >>>>>
> >>>>>
> >>>>> Now:
> >>>>>
> >>>>> mult =3D 10000
> >>>>> offset =3D 200
> >>>>> test_freq =3D 9800
> >>>>> freq =3D 9800
> >>>>> div =3D 9800 / 10000 + 1 =3D 0 + 1 =3D 1
> >>>>>
> >>>>> ...and then you'll loop again with "div =3D 1", won't you? ...or di=
d I
> >>>>> get something wrong in my analysis? This is the reason my proposed
> >>>>> algorithm had two loops.
> >>>>>
> >>>>>
> >>>> I went back to your proposed algorithm and made couple of simple
> >>> changes, and it seemed like what we need.
> >>>> a) look only for exact match once a clock rate within tolerance is
> >>>> found
> >>>> b) swap test_freq and freq at end of while loops to make it run as
> >>>> desired
> >>>>
> >>>>
> >>>>          maxdiv =3D CLK_DIV_MSK >> CLK_DIV_SHFT;
> >>>>          div =3D 1;
> >>>>
> >>>>          while (div < maxdiv) {
> >>>>                  mult =3D (unsigned long long)div * desired_clk;
> >>>>                  if (mult !=3D (unsigned long)mult)
> >>>>                          break;
> >>>>
> >>>>                  if (ser_clk)
> >>>>                          offset =3D 0;
> >>>>                  =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3Da=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> >>>>                  else
> >>>>                          offset =3D div_u64(mult * percent_tol, 100)=
;
> >>>>
> >>>>                  /*
> >>>>                   * Loop requesting (freq - 2%) and possibly (freq).
> >>>>                   *
> >>>>                   * We'll keep track of the lowest freq inexact matc=
h we found
> >>>>                   * but always try to find a perfect match. NOTE: th=
is algorithm
> >>>>                   * could miss a slightly better freq if there's mor=
e than one
> >>>>                   * freq between (freq - 2%) and (freq) but (freq) c=
an't be made
> >>>>                   * exactly, but that's OK.
> >>>>                   *
> >>>>                   * This absolutely relies on the fact that the Qual=
comm clock
> >>>>                   * driver always rounds up.
> >>>>                   */
> >>>>                  test_freq =3D mult - offset;
> >>>>                  while (test_freq <=3D mult) {
> >>>>                          freq =3D clk_round_rate(clk, test_freq);
> >>>>
> >>>>                          /*
> >>>>                           * A dead-on freq is an insta-win. This imp=
licitly
> >>>>                           * handles when "freq =3D=3D mult"
> >>>>                           */
> >>>>                          if (!(freq % desired_clk)) {
> >>>>                                  *clk_div =3D freq / desired_clk;
> >>>>                                  return freq;
> >>>>                          }
> >>>>
> >>>>                          /*
> >>>>                           * Only time clock framework doesn't round =
up is if
> >>>>                           * we're past the max clock rate. We're don=
e searching
> >>>>                           * if that's the case.
> >>>>                           */
> >>>>                          if (freq < test_freq)
> >>>>                                  return ser_clk;
> >>>>
> >>>>                          /* Save the first (lowest freq) within tole=
rance */
> >>>>                          if (!ser_clk && freq <=3D mult + offset) {
> >>>>                                  ser_clk =3D freq;
> >>>>                                  *clk_div =3D div;
> >>>>                          }
> >>>>
> >>>>                          /*
> >>>>                           * If we already rounded up past mult then =
this will
> >>>>                           * cause the loop to exit. If not then this=
 will run
> >>>>                           * the loop a second time with exactly mult=
.
> >>>>                           */
> >>>>                          test_freq =3D max(test_freq + 1, mult);
> >>>>                                                       =3D=3D=3D=3Db=
=3D=3D=3D=3D
> >>>>                  }
> >>>>
> >>>>                  /*
> >>>>                   * freq will always be bigger than mult by at least=
 1.
> >>>>                   * That means we can get the next divider with a DI=
V_ROUND_UP.
> >>>>                   * This has the advantage of skipping by a whole bu=
nch of divs
> >>>>                   * If the clock framework already bypassed them.
> >>>>                   */
> >>>>                  div =3D DIV_ROUND_UP(freq, desired_clk);
> >>>>                                                         =3D=3D=3Db=
=3D=3D
> >>>>          }
> >>>>
> >>>>
> >>>> Will also drop exact_match now.
> >>>>
> >>>> Will upload v3 after testing.
> >>> The more I've been thinking about it, the more I wonder if we even ne=
ed the
> >>> special case of looking for an exact match at all. It feels like we s=
hould choose
> >>> one: we either look for the best match or we look for the one with th=
e
> >>> lowest clock source rate. The weird half-half approach that we have r=
ight
> >>> now feels like over-engineering and complicates things.
> >>>
> >>> How about this (again, only lightly tested). Worst case if we _truly_=
 need a
> >>> close-to-exact match we could pass a tolerance of 0 in and we'd get
> >>> something that's nearly exact, though I'm not suggesting we actually =
do that.
> >>> If we think 2% is good enough then we should just accept the first (a=
nd
> >>> lowest clock rate) 2% match we find.
> >>>
> >>>      abs_tol =3D div_u64((u64)desired_clk * percent_tol, 100);
> >>>      maxdiv =3D CLK_DIV_MSK >> CLK_DIV_SHFT;
> >>>      div =3D 1;
> >>>      while (div <=3D maxdiv) {
> >>>          mult =3D (u64)div * desired_clk;
> >>>          if (mult !=3D (unsigned long)mult)
> >>>              break;
> >>>
> >>>          offset =3D div * abs_tol;
> >>>          freq =3D clk_round_rate(clk, mult - offset);
> >>>
> >>>          /* Can only get lower if we're done */
> >>>          if (freq < mult - offset)
> >>>              break;
> >>>
> >>>          /*
> >>>           * Re-calculate div in case rounding skipped rates but we
> >>>           * ended up at a good one, then check for a match.
> >>>           */
> >>>          div =3D DIV_ROUND_CLOSEST(freq, desired_clk);
> >>>          achieved =3D DIV_ROUND_CLOSEST(freq, div);
> >>>          if (achieved <=3D desired_clk + abs_tol &&
> >>>              achieved >=3D desired_clk - abs_tol) {
> >>>              *clk_div =3D div;
> >>>              return freq;
> >>>          }
> >>>
> >>>          /*
> >>>           * Always increase div by at least one, but we'll go more th=
an
> >>>           * one if clk_round_rate() gave us something higher.
> >>>           */
> >>>          div =3D DIV_ROUND_UP(max(freq, (unsigned long)mult) + 1, des=
ired_clk);
> >> Wouldn=E2=80=99t DIV_ROUND_UP(freq, desired_clk) suffice here?
> >> freq >=3D mult-offset, else we would have hit break.
> > No. As you say, freq >=3D "mult-offset". That means that freq could be
> > =3D=3D "mult-offset", right? If offset > 0 then freq could be < mult. T=
hen
> > your DIV_ROUND_UP() would just take you right back to where you
> > started the loop with and you'd end up with an infinite loop, wouldn't
> > you?
> >
> Probably No.
>
> ( (freq >=3D mult-offset) && (freq <=3D mult) ) =3D>
>
> ( (freq >=3D mult-offset) && (freq <=3D mult+offset) )
>
> would mean that
>
> div =3D DIV_ROUND_CLOSEST(freq, desired_clk);
> evaluates to original div and we are within tolerance and hence we can re=
turn and hence don't even reach DIV_ROUND_UP?
>
> Please note that freq can skip any multiples and land up anywhere.
>
> As long as it has not gone beyond clock rate table, either it lands
> within tolerance of nearest multiple of desired_clk (in which case we
> return)
>
> OR
>
> We move on to next div =3D (freq/desired_clk + 1)

Ah, you are correct. So just:

div =3D DIV_ROUND_UP(freq, desired_clk);

...because freq _has_ to be greater than mult. If it was < "mult -
offset" we would have ended the loop. If it was between "mult -
offset" and "mult + offset" (inclusive) then we would have success. So
freq must be > "mult + offset" at the end of the loop.

-Doug