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Date:   Wed, 06 Jul 2022 21:49:43 +0100
From:   "Jiaxun Yang" <jiaxun.yang@flygoat.com>
To:     "Qi Hu" <huqi@loongson.cn>, "Xi Ruoyao" <xry111@xry111.site>,
        "Huacai Chen" <chenhuacai@kernel.org>
Cc:     "Xuerui Wang" <kernel@xen0n.name>, loongarch@lists.linux.dev,
        LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] LoongArch: Clean useless vcsr in loongarch_fpu.
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=E5=9C=A82022=E5=B9=B47=E6=9C=886=E6=97=A5=E4=B8=83=E6=9C=88 =E4=B8=8A=E5=
=8D=885:00=EF=BC=8CQi Hu=E5=86=99=E9=81=93=EF=BC=9A
> On 2022/7/6 10:51, Xi Ruoyao wrote:
>> On Wed, 2022-07-06 at 10:35 +0800, Huacai Chen wrote:
>>
>>> Maybe Xuerui and Ruoyao have some misunderstanding. LSX/LASX will
>>> surely be upstream, this has nothing to do with cleanup VCSR16.
>>> Because FP/LSX/LASX share the same control bits in FCSR now.
>> My guess:
>>
>> Almost all behavior of vector unit is controlled by FCSR (for example,
>> the rounding of both FPU and vector unit should be controlled by FCSR
>> altogether), except one bit similar to the bit 24 of MSACSR ("flush to
>> zero") is in VCSR [^1].  And "flush to zero" is not really useful so =
it
>> will be removed in 3A6000, and we'll not use it for 3A5000.
> Actually, flush to zero has been removed in 3A5000.
>>
>> [^1]: A more bold guess: the hardware engineers could have just said
>> "let's wire this register called MSACSR in GS464V as FCSR16/VCSR in
>> LA464, maybe it will be useful and who knows?"  But now in practice i=
t's
>> not useful.
>>
>> Am I correct?
> The hardware(LA464) has removed the vcsr("has but not use" is=20
> incorrect), and here are some details:
>
> - For all FP operations, including LSX/LASX, they are controlled by=20
> fcsr0/1/2/3.
>
> - For LSX/LASX other operations, they are *not* controlled by any othe=
r=20
> CSR now. And fcsr16 to fcsr31 are reserved to control these operations=20
> (now they are *undefined*).
Sorry but what do you meant by =E2=80=9Cthese=E2=80=9D here?
If it means LSX/LASX, are you trying to say that future chip=E2=80=99s L=
SX/LASX won=E2=80=99t be
compatible with present 3A5000? As your said fcsr16 and fcsr31 are undef=
ined
for now.

Thanks
-

>
> - Flush to zero(MSACSR.FS) is removed and not supported.
>
> - If you use "movfcsr2gr" to read the fcsr16, the value is *UNDEFINED*.

--=20
- Jiaxun