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Date:   Thu, 07 Jul 2022 10:51:33 +0100
Message-ID: <87a69lmesa.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Rob Herring <robh@kernel.org>
Cc:     "Lad, Prabhakar" <prabhakar.csengg@gmail.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Sagar Kadam <sagar.kadam@sifive.com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        LKML <linux-kernel@vger.kernel.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Phil Edworthy <phil.edworthy@renesas.com>,
        Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH RFC 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC
In-Reply-To: <20220706215827.GA572635-robh@kernel.org>
References: <20220524172214.5104-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
        <20220524172214.5104-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
        <20220605142333.GA3439339-robh@kernel.org>
        <CA+V-a8smk8TqyWpm1KXo-3dKnCAodKsiYsaqnK_3ubfXE9YauQ@mail.gmail.com>
        <20220706215827.GA572635-robh@kernel.org>
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On Wed, 06 Jul 2022 22:58:27 +0100,
Rob Herring <robh@kernel.org> wrote:
> 
> On Fri, Jun 24, 2022 at 10:59:40AM +0100, Lad, Prabhakar wrote:
> > Hi Rob,
> > 
> > Thank you for the review.
> > 
> > On Sun, Jun 5, 2022 at 3:23 PM Rob Herring <robh@kernel.org> wrote:
> > >
> > > On Tue, May 24, 2022 at 06:22:13PM +0100, Lad Prabhakar wrote:
> > > > Document Renesas RZ/Five (R9A07G043) SoC.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > >  .../sifive,plic-1.0.0.yaml                    | 38 +++++++++++++++++--
> > > >  1 file changed, 35 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > > index 27092c6a86c4..78ff31cb63e5 100644
> > > > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > > @@ -28,7 +28,10 @@ description:
> > > >
> > > >    While the PLIC supports both edge-triggered and level-triggered interrupts,
> > > >    interrupt handlers are oblivious to this distinction and therefore it is not
> > > > -  specified in the PLIC device-tree binding.
> > > > +  specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
> > > > +  but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
> > > > +  to specify the interrupt type as the flow for EDGE interrupts is different
> > > > +  compared to LEVEL interrupts.
> > > >
> > > >    While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
> > > >    "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
> > > > @@ -57,6 +60,7 @@ properties:
> > > >            - enum:
> > > >                - allwinner,sun20i-d1-plic
> > > >            - const: thead,c900-plic
> > > > +      - const: renesas-r9a07g043-plic
> 
> Also, this should be 'renesas,r9...'
> 
> > > >
> > > >    reg:
> > > >      maxItems: 1
> > > > @@ -64,8 +68,7 @@ properties:
> > > >    '#address-cells':
> > > >      const: 0
> > > >
> > > > -  '#interrupt-cells':
> > > > -    const: 1
> > > > +  '#interrupt-cells': true
> > > >
> > > >    interrupt-controller: true
> > > >
> > > > @@ -91,6 +94,35 @@ required:
> > > >    - interrupts-extended
> > > >    - riscv,ndev
> > > >
> > > > +if:
> > > > +  properties:
> > > > +    compatible:
> > > > +      contains:
> > > > +        const: renesas-r9a07g043-plic
> > > > +then:
> > > > +  properties:
> > > > +    clocks:
> > > > +      maxItems: 1
> > > > +
> > > > +    resets:
> > > > +      maxItems: 1
> > > > +
> > > > +    power-domains:
> > > > +      maxItems: 1
> > >
> > > Did you test this? The above properties won't be allowed because of
> > > additionalProperties below. You need to change it to
> > > 'unevaluatedProperties' or move these to the top level.
> > >
> > Yes I have run the dt_binding check.
> > 
> > So with the below diff it does complain about the missing properties.
> > 
> > prasmi@prasmi:~/work/renasas/renesas-drivers$ git diff
> > Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > index 20ded037d444..bb14a4b1ec0a 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > @@ -130,7 +130,7 @@ examples:
> >      plic: interrupt-controller@c000000 {
> >        #address-cells = <0>;
> >        #interrupt-cells = <1>;
> > -      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
> > +      compatible = "renesas-r9a07g043-plic";
> >        interrupt-controller;
> >        interrupts-extended = <&cpu0_intc 11>,
> >                              <&cpu1_intc 11>, <&cpu1_intc 9>,
> > prasmi@prasmi:~/work/renasas/renesas-drivers$ make ARCH=riscv
> > CROSS_COMPILE=riscv64-linux-gnu- dt_binding_check
> >   LINT    Documentation/devicetree/bindings
> >   CHKDT   Documentation/devicetree/bindings/processed-schema.json
> >   SCHEMA  Documentation/devicetree/bindings/processed-schema.json
> >   DTEX    Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.example.dts
> >   DTC     Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.example.dtb
> >   CHECK   Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.example.dtb
> > /home/prasmi/work/renasas/renesas-drivers/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.example.dtb:
> > interrupt-controller@c000000: #interrupt-cells:0:0: 2 was expected
> >     From schema:
> > /home/prasmi/work/renasas/renesas-drivers/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > /home/prasmi/work/renasas/renesas-drivers/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.example.dtb:
> > interrupt-controller@c000000: 'clocks' is a required property
> >     From schema:
> > /home/prasmi/work/renasas/renesas-drivers/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > /home/prasmi/work/renasas/renesas-drivers/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.example.dtb:
> > interrupt-controller@c000000: 'resets' is a required property
> >     From schema:
> > /home/prasmi/work/renasas/renesas-drivers/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > /home/prasmi/work/renasas/renesas-drivers/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.example.dtb:
> > interrupt-controller@c000000: 'power-domains' is a required property
> >     From schema:
> > /home/prasmi/work/renasas/renesas-drivers/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > prasmi@prasmi:~/work/renasas/renesas-drivers$
> > prasmi@prasmi:~/work/renasas/renesas-drivers$
> > 
> > Is there something I'm missing here?
> 
> You've said these properties are required, but you didn't add them.
> 
> If you don't have the above 3 properties, then it's not going to 
> complain that they are present. But it will when you do add them for the 
> reason I gave.

Can you please have a look at the latest instance[1][2] of this
series, as posted by Samuel? I've provisionally queued it, but only on
the provision that you would eventually ack these patches.

Thanks,

	M.

[1] https://lore.kernel.org/r/20220630100241.35233-2-samuel@sholland.org
[2] https://lore.kernel.org/r/20220630100241.35233-4-samuel@sholland.org

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