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Date:   Thu, 07 Jul 2022 13:51:35 +0100
Message-ID: <87zghlkrvs.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Jianmin Lv <lvjianmin@loongson.cn>,
        Rafael J Wysocki <rafael@kernel.org>,
        Robert Moore <robert.moore@intel.com>
Cc:     Thomas Gleixner <tglx@linutronix.de>, linux-kernel@vger.kernel.org,
        Hanjun Guo <guohanjun@huawei.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Jiaxun Yang <jiaxun.yang@flygoat.com>,
        Huacai Chen <chenhuacai@loongson.cn>
Subject: Re: [PATCH V14 00/15] irqchip: Add LoongArch-related irqchip drivers
In-Reply-To: <1656837932-18257-1-git-send-email-lvjianmin@loongson.cn>
References: <1656837932-18257-1-git-send-email-lvjianmin@loongson.cn>
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+ Rafael, Robert

On Sun, 03 Jul 2022 09:45:17 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
> 
> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
> boot protocol LoongArch-specific interrupt controllers (similar to APIC)
> are already added in the ACPI Specification 6.5(which may be published in
> early June this year and the board is reviewing the draft).

Can the ACPI/ACPICA maintainers eyeball patch #1 in this series[1]? It
adds some new, yet unpublished ACPI MADT updates, and I need an Ack on
that before considering taking this series.

Patches 2 and 3 could also do with an Ack from the ACPI maintainers
(though Hanjun did review an earlier version).

Thanks,
	M.

[1] https://lore.kernel.org/r/1656837932-18257-2-git-send-email-lvjianmin@loongson.cn

-- 
Without deviation from the norm, progress is not possible.