Received: by 2002:ad5:4acb:0:0:0:0:0 with SMTP id n11csp4116543imw; Thu, 7 Jul 2022 13:03:59 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vKqwTjAhiBf/TlbVmcAcC5T7unO9W2QM5N+wYluWiHiEcOieUIHT8FphTkNEeDpg9ML0kB X-Received: by 2002:a17:90b:3a8d:b0:1ef:7d4:6a5f with SMTP id om13-20020a17090b3a8d00b001ef07d46a5fmr7058590pjb.139.1657224239397; Thu, 07 Jul 2022 13:03:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657224239; cv=none; d=google.com; s=arc-20160816; b=OG0SMXvAQQKDUiVTtqyyNb6dhnWqPeTTMrP2ERs1xI6PL6Rp9ryiRJZcs6jGA0n7gE NE6vGOWhhKksniWK8mCDjy5+Cp4ob56Da1zyq0iLyEb9/OUOkVlPhCj74+owRdsBF5xA zmmH3rGEEUUM/6cfB2lJyaV2BC/VSDSTdE83kEWvF4OBhpYhfDp9f7q+OoUg99jblHZf FCK+0j3SjKzRY2TF6yQ52zKxxyZdFM6vk+HTITzBoTPgKKKSiL9IuWx8AS9yKzTxXS2y Hnr8Jmoj3Qvf+OF9tF1ZdA6fG/QCoFuvnucJaO2HKxDMtltzMD2M07QDZG6Tw40yB5vV /sNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=97AxfpAWfhGkMoo8Yg3C7zAZZuUe0uLsnJoPG2mxaas=; b=GMySOd+lYKsNYFNqYcTejsqv11S1QkFB+BL7ZX8/NpKvQX11GezqnmJsoV0N7+i+M3 J4+0LD8jBLuF1BgewVlUtnQwseu8epgQGPBJDqxhCHMVtGk+PnAfE0xkdWNe3wpiboNN TDXdxDset/MHx3g/T0JpOIq0r+/45DS6DVluIqINJZDcvRb9JJhSYeuorIyWAgQlyVGT a/i9Z59WLmqGkGNuudA2IlAvwMtk7NrFSXPdc7TNDIBCXTgOYb+Vd8DUza+798PuNHmR mRq9tcVXnhqQNff6svMWl45AFX19VD8v8lBl5blmT9a932pU1ESpyRj6Q5KRbOuuEQ5M nHBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=a5QRanr2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id oc6-20020a17090b1c0600b001ef0598c9a5si35729718pjb.141.2022.07.07.13.03.20; Thu, 07 Jul 2022 13:03:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=a5QRanr2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236596AbiGGTq7 (ORCPT + 99 others); Thu, 7 Jul 2022 15:46:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236512AbiGGTqu (ORCPT ); Thu, 7 Jul 2022 15:46:50 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DA3757242; Thu, 7 Jul 2022 12:46:49 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id sb34so34153502ejc.11; Thu, 07 Jul 2022 12:46:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=97AxfpAWfhGkMoo8Yg3C7zAZZuUe0uLsnJoPG2mxaas=; b=a5QRanr2WKmBO3i7q2e/BelNFTX9jLNDQUKpi52hdVULwjL/b04H77iS/RMIw8j4op pByPDV9v/KHtjRTy6VN5vu4EuTuS3blM3591Mr+eghWhYDhLc6SZKAxKq8aMGOwZo2AD nIppZlcl9kSXfy7ioykZLtq9FzgApUKOH/rP6Q5hFSy3hEfwxiZ3wa3i+1HDbyAWCYtt ZWTMPs5KLX99aeXEI48jPp54TYi4YGdbr7QoS6YclSkxAK37aFs7IbSWaBOL2VSUbuYX QCaa9mKp+jgEgMdcTE/rFkPgnhWB8MJ3yZwUv5rvE1Eh0XR0mTuFdQiQxASzgn5X9dpH eayQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=97AxfpAWfhGkMoo8Yg3C7zAZZuUe0uLsnJoPG2mxaas=; b=GyUgY2VhZUwb9jWnAd37RTTQfwEJArqKqo8xWSbD0DVX/UUYdb6Ts9XkXQiIWjUVCG tp3Z1luuS3HAmp7qbsfm4qv1jxuq0bRZ08fEXYTTg8ha9j7tUNai2c6J3FKKGjhKoPKs A0p+s2qXDjfH52p0frkM4Ubq39ruzOj6wfrNlvslfTVKKtZa9XJBtIx9+IYhopU+SLfO 5Q90R3G+UJW6ON7apMG7zVJ8OHTqJ8wnjmfE5z0G7km94IzjLX7+kC0hx/DSr5NV9MmO uFWQX5ERbVNZpxjFEMcrNzGKwDhuoUKNbg9Lp6d+hzEyF9zO2GAZpXudaSvjIEamqQTT MCag== X-Gm-Message-State: AJIora9DQz0UCz5GAZWAF1D+66D5se7WYRDEyYPLKs8e/liq0RalN0QF s/0L2mAe4P6lWfweaYhgrGerfq4J1Fs= X-Received: by 2002:a17:907:da7:b0:726:9c0b:708b with SMTP id go39-20020a1709070da700b007269c0b708bmr47278750ejc.595.1657223208689; Thu, 07 Jul 2022 12:46:48 -0700 (PDT) Received: from localhost (92.40.202.166.threembb.co.uk. [92.40.202.166]) by smtp.gmail.com with ESMTPSA id f16-20020a056402329000b0043a83f77b59sm5266723eda.48.2022.07.07.12.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 12:46:48 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/11] ASoC: jz4740-i2s: Align macro values and sort includes Date: Thu, 7 Jul 2022 20:46:50 +0100 Message-Id: <20220707194655.312892-7-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> References: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some purely cosmetic changes: line up all the macro values to make things easier to read and sort the includes alphabetically. Acked-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 72 +++++++++++++++++------------------ 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index d0791dfa9c7b..0dcc658b3784 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -4,6 +4,9 @@ */ #include +#include +#include +#include #include #include #include @@ -13,11 +16,6 @@ #include #include -#include -#include - -#include - #include #include #include @@ -35,39 +33,39 @@ #define JZ_REG_AIC_CLK_DIV 0x30 #define JZ_REG_AIC_FIFO 0x34 -#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) -#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) -#define JZ_AIC_CONF_I2S BIT(4) -#define JZ_AIC_CONF_RESET BIT(3) -#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) -#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) -#define JZ_AIC_CONF_ENABLE BIT(0) - -#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) -#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) -#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) -#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) -#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) -#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) -#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) +#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) +#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) +#define JZ_AIC_CONF_I2S BIT(4) +#define JZ_AIC_CONF_RESET BIT(3) +#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) +#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) +#define JZ_AIC_CONF_ENABLE BIT(0) + +#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) +#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) +#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) +#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) +#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) +#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) +#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) #define JZ_AIC_CTRL_FLUSH BIT(8) -#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) -#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) -#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) -#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) -#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) -#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) -#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) - -#define JZ4760_AIC_CTRL_TFLUSH BIT(8) -#define JZ4760_AIC_CTRL_RFLUSH BIT(7) - -#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) -#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) -#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) -#define JZ_AIC_I2S_FMT_MSB BIT(0) - -#define JZ_AIC_I2S_STATUS_BUSY BIT(2) +#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) +#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) +#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) +#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) +#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) +#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) +#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) + +#define JZ4760_AIC_CTRL_TFLUSH BIT(8) +#define JZ4760_AIC_CTRL_RFLUSH BIT(7) + +#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) +#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) +#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) +#define JZ_AIC_I2S_FMT_MSB BIT(0) + +#define JZ_AIC_I2S_STATUS_BUSY BIT(2) struct i2s_soc_info { struct snd_soc_dai_driver *dai; -- 2.35.1