Received: by 2002:ad5:4acb:0:0:0:0:0 with SMTP id n11csp4279977imw; Thu, 7 Jul 2022 16:10:54 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tlyL5cWMH0tjXQ18XN8CPDRlxGF7zcE7PsUB4SgEy6aqK46qjyIaxqF6bfepVI5oMg8of7 X-Received: by 2002:a17:90b:38ce:b0:1ef:c5bd:e2bd with SMTP id nn14-20020a17090b38ce00b001efc5bde2bdmr304131pjb.149.1657235453994; Thu, 07 Jul 2022 16:10:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657235453; cv=none; d=google.com; s=arc-20160816; b=ekSKPm3EYUGTwuYZMYRKFsIh4Mla6+7Q2sIoiEW498gWcAR9YgpbWiDok/wrT3DqGn D2amasdY0VIADmO8BP2O90Jy0NuBDzg9XYFvcciR1lpW1Ws8Kdl+ikplVYhpDKIpIFZw 8XCXY81qAVCZcAuDk6gmXVFZ2B+RrgXxl2QCYnSeonB5oqneE4pOabePyQ51Q4/Wokts gtTDWZVZakGZxxOkTS7qKjDhbMOhD8udDLyos8oi/xTQD4c1/1ymer0wjsrbIafC9+/0 Ij2jhcmfO6x/BfjuTByuEgAEEfgzbSqn27vKnzxidNmfmWtGHMRqc8MgNu3Q2PffC/IX Ut3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cp4kFfIV9vxNzkxwPVJY1RIkCxRVw29SgQ0nN5WqYjM=; b=SVH+rJSfhn1BNrR0RGokkL8OdFw60bgtTFCsKQiCB2AP6A2tumrZgpnRlVb9NE3v7+ ToCmG07xdvYVjqmnrNW3tlsxgeeFSQ8nRjbAMZ4oeFHq12fCJbLdc5Cq4kfwWT+mfnCs O/Ee+w3qL6Rhbtl3IbhY9eI9DHxFejHrB1KQRX0T5CUb/6mMVwjnGfwa5w9NEIBLkO0Z T6YE4YEQrGY9h0jKc9vfN3Ot1972m5yx/j0jkXTSsnZk/ZE6/CkNPL5IOTIdZGi+k+7O xaBkrTSdQLyqNttsYNWlfvvjzJvh+OOMJZF1tSKPMjdqhcK7y3h4SW2zw7cn2RInm/83 TOwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jJNz4Qmf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e8-20020a056a001a8800b00525b5f75454si46896971pfv.121.2022.07.07.16.10.37; Thu, 07 Jul 2022 16:10:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jJNz4Qmf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237046AbiGGWa0 (ORCPT + 99 others); Thu, 7 Jul 2022 18:30:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236730AbiGGWaX (ORCPT ); Thu, 7 Jul 2022 18:30:23 -0400 Received: from mail-qt1-x832.google.com (mail-qt1-x832.google.com [IPv6:2607:f8b0:4864:20::832]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF94F65D67 for ; Thu, 7 Jul 2022 15:30:21 -0700 (PDT) Received: by mail-qt1-x832.google.com with SMTP id he28so24906620qtb.13 for ; Thu, 07 Jul 2022 15:30:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cp4kFfIV9vxNzkxwPVJY1RIkCxRVw29SgQ0nN5WqYjM=; b=jJNz4QmfJij1m5k1Z3WHbkakIK/EEmazjOfG3VCc25VR3Ml74OCYQ4y1ulHaZfPNao 7WKFNeHCSYyiKJIZ5DxPBPf6QA/DMC7UBXohxvoKjcQaLewy2umh5vP4CQ07irJqcEVX LOjAzOH87+b+lQZPAs75S8ZoFvszBFrPvoaCqNUhGZ8FCCcQ0J1DzJyqiKDM87rLRYBb Aqy1O0jXjy+Qwzzw0f8S0/3nxvf6ZbgSOls+K2iBPKLYUnwkIQA4PJSlt+hw/viG+P2O x1I3kbfiy3YHiidJqDHDilEvV/livKcnNTx5AfoJEYjWXUUzirTyrkmEF6E7cp7Qp0Wu EKxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cp4kFfIV9vxNzkxwPVJY1RIkCxRVw29SgQ0nN5WqYjM=; b=Cj2ixqx1bYrKBVbCGKFHNuFTgelocnotxlyQZdH9ajpUwoysoU9GA2i0hm0KrxB6A+ Zej40wv1FHbFGM1ct8k+E/csZSWjXma00xzF9TrH7tfbiiBNHKlo2IdPZqY5M0y6c1wf KFVrezcZKfOFgPvy7rumAFL+FIy1twfG/D8ivzyFfYR2b4f056pRFuwYr20BfAR/qw2k oUPf5yHEmUFmBundTgCSchGFxoTSPsjn3aPXN/UM0wCgJoPc3RMajRa4/1JYFFwtqHwp H57G4LE9qnN79kXCD74SNdV78v31I0+C7sOVeANQwdHrEJbwrM6DoQkZKDYRVnit0+OM gCVA== X-Gm-Message-State: AJIora/Gc/zL5KkhNdJF3txKZOm+DjksqXHKv/STOVeU37HhM0HjfEY8 pgiQirEZz4hzfIqFIotL5gJc7Q== X-Received: by 2002:a05:6214:21ec:b0:470:3f54:e846 with SMTP id p12-20020a05621421ec00b004703f54e846mr328601qvj.58.1657233020932; Thu, 07 Jul 2022 15:30:20 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id e22-20020ac84b56000000b0031e9bd3586esm1527747qts.79.2022.07.07.15.30.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 15:30:20 -0700 (PDT) From: William Breathitt Gray To: jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, William Breathitt Gray , Fred Eckert Subject: [PATCH v2 1/2] iio: adc: stx104: Implement and utilize register structures Date: Thu, 7 Jul 2022 13:21:24 -0400 Message-Id: <8cb91d5b53e57b066120e42ea07000d6c7ef5543.1657213745.git.william.gray@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.5 required=5.0 tests=BAYES_00,DATE_IN_PAST_03_06, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Reduce magic numbers and improve code readability by implementing and utilizing named register data structures. Tested-by: Fred Eckert Signed-off-by: William Breathitt Gray --- drivers/iio/adc/stx104.c | 74 +++++++++++++++++++++++++++------------- 1 file changed, 50 insertions(+), 24 deletions(-) diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c index 7552351bfed9..48a91a95e597 100644 --- a/drivers/iio/adc/stx104.c +++ b/drivers/iio/adc/stx104.c @@ -16,6 +16,7 @@ #include #include #include +#include #define STX104_OUT_CHAN(chan) { \ .type = IIO_VOLTAGE, \ @@ -44,14 +45,36 @@ static unsigned int num_stx104; module_param_hw_array(base, uint, ioport, &num_stx104, 0); MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses"); +/** + * struct stx104_reg - device register structure + * @ssr_ad: Software Strobe Register and ADC Data + * @achan: ADC Channel + * @dio: Digital I/O + * @dac: DAC Channels + * @cir_asr: Clear Interrupts and ADC Status + * @acr: ADC Control + * @pccr_fsh: Pacer Clock Control and FIFO Status MSB + * @acfg: ADC Configuration + */ +struct stx104_reg { + u16 ssr_ad; + u8 achan; + u8 dio; + u16 dac[2]; + u8 cir_asr; + u8 acr; + u8 pccr_fsh; + u8 acfg; +}; + /** * struct stx104_iio - IIO device private data structure * @chan_out_states: channels' output states - * @base: base port address of the IIO device + * @reg: I/O address offset for the device registers */ struct stx104_iio { unsigned int chan_out_states[STX104_NUM_OUT_CHAN]; - void __iomem *base; + struct stx104_reg __iomem *reg; }; /** @@ -64,7 +87,7 @@ struct stx104_iio { struct stx104_gpio { struct gpio_chip chip; spinlock_t lock; - void __iomem *base; + u8 __iomem *base; unsigned int out_state; }; @@ -72,6 +95,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { struct stx104_iio *const priv = iio_priv(indio_dev); + struct stx104_reg __iomem *const reg = priv->reg; unsigned int adc_config; int adbu; int gain; @@ -79,7 +103,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_HARDWAREGAIN: /* get gain configuration */ - adc_config = ioread8(priv->base + 11); + adc_config = ioread8(®->acfg); gain = adc_config & 0x3; *val = 1 << gain; @@ -91,24 +115,26 @@ static int stx104_read_raw(struct iio_dev *indio_dev, } /* select ADC channel */ - iowrite8(chan->channel | (chan->channel << 4), priv->base + 2); + iowrite8(chan->channel | (chan->channel << 4), ®->achan); - /* trigger ADC sample capture and wait for completion */ - iowrite8(0, priv->base); - while (ioread8(priv->base + 8) & BIT(7)); + /* trigger ADC sample capture by writing to the 8-bit + * Software Strobe Register and wait for completion + */ + iowrite8(0, ®->ssr_ad); + while (ioread8(®->cir_asr) & BIT(7)); - *val = ioread16(priv->base); + *val = ioread16(®->ssr_ad); return IIO_VAL_INT; case IIO_CHAN_INFO_OFFSET: /* get ADC bipolar/unipolar configuration */ - adc_config = ioread8(priv->base + 11); + adc_config = ioread8(®->acfg); adbu = !(adc_config & BIT(2)); *val = -32768 * adbu; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: /* get ADC bipolar/unipolar and gain configuration */ - adc_config = ioread8(priv->base + 11); + adc_config = ioread8(®->acfg); adbu = !(adc_config & BIT(2)); gain = adc_config & 0x3; @@ -130,16 +156,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev, /* Only four gain states (x1, x2, x4, x8) */ switch (val) { case 1: - iowrite8(0, priv->base + 11); + iowrite8(0, &priv->reg->acfg); break; case 2: - iowrite8(1, priv->base + 11); + iowrite8(1, &priv->reg->acfg); break; case 4: - iowrite8(2, priv->base + 11); + iowrite8(2, &priv->reg->acfg); break; case 8: - iowrite8(3, priv->base + 11); + iowrite8(3, &priv->reg->acfg); break; default: return -EINVAL; @@ -153,7 +179,7 @@ static int stx104_write_raw(struct iio_dev *indio_dev, return -EINVAL; priv->chan_out_states[chan->channel] = val; - iowrite16(val, priv->base + 4 + 2 * chan->channel); + iowrite16(val, &priv->reg->dac[chan->channel]); return 0; } @@ -307,15 +333,15 @@ static int stx104_probe(struct device *dev, unsigned int id) } priv = iio_priv(indio_dev); - priv->base = devm_ioport_map(dev, base[id], STX104_EXTENT); - if (!priv->base) + priv->reg = devm_ioport_map(dev, base[id], STX104_EXTENT); + if (!priv->reg) return -ENOMEM; indio_dev->info = &stx104_info; indio_dev->modes = INDIO_DIRECT_MODE; /* determine if differential inputs */ - if (ioread8(priv->base + 8) & BIT(5)) { + if (ioread8(&priv->reg->cir_asr) & BIT(5)) { indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff); indio_dev->channels = stx104_channels_diff; } else { @@ -326,14 +352,14 @@ static int stx104_probe(struct device *dev, unsigned int id) indio_dev->name = dev_name(dev); /* configure device for software trigger operation */ - iowrite8(0, priv->base + 9); + iowrite8(0, &priv->reg->acr); /* initialize gain setting to x1 */ - iowrite8(0, priv->base + 11); + iowrite8(0, &priv->reg->acfg); /* initialize DAC output to 0V */ - iowrite16(0, priv->base + 4); - iowrite16(0, priv->base + 6); + iowrite16(0, &priv->reg->dac[0]); + iowrite16(0, &priv->reg->dac[1]); stx104gpio->chip.label = dev_name(dev); stx104gpio->chip.parent = dev; @@ -348,7 +374,7 @@ static int stx104_probe(struct device *dev, unsigned int id) stx104gpio->chip.get_multiple = stx104_gpio_get_multiple; stx104gpio->chip.set = stx104_gpio_set; stx104gpio->chip.set_multiple = stx104_gpio_set_multiple; - stx104gpio->base = priv->base + 3; + stx104gpio->base = &priv->reg->dio; stx104gpio->out_state = 0x0; spin_lock_init(&stx104gpio->lock); -- 2.36.1