Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Fri, 8 Jul 2022 10:43:32 +0530
From:   Vinod Koul <vkoul@kernel.org>
To:     Liu Ying <victor.liu@nxp.com>
Cc:     linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        kishon@ti.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org,
        s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
        linux-imx@nxp.com, krzysztof.kozlowski@linaro.org
Subject: Re: [PATCH v4 0/3] phy: freescale: Add i.MX8qm Mixel LVDS PHY support
Message-ID: <Yse8/MjjmShPpltv@matsya>
References: <20220706034810.2352641-1-victor.liu@nxp.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20220706034810.2352641-1-victor.liu@nxp.com>
Precedence: bulk

On 06-07-22, 11:48, Liu Ying wrote:
> Hi,
> 
> This series aims to add Freescale i.MX8qm LVDS PHY driver and dt-binding
> support.
> 
> The PHY IP is from Mixel, Inc.
> The PHY IP supports two LVDS PHYs, thus two LVDS channels.
> 
> Each LVDS PHY may work by itself to support a LVDS display device.
> 
> When two LVDS PHYs are enabled simultaneously, PHY configurations and reference
> clock rate have to be the same since there is only one set of PHY registers.
> In this case, the two LVDS PHYs are usually used to support a dual LVDS link
> display device, one as master PHY and the other as slave PHY.

Applied, thanks

-- 
~Vinod