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[2620:137:e000::1:20]) by mx.google.com with ESMTP id pm11-20020a17090b3c4b00b001ec93087883si2551801pjb.121.2022.07.08.05.26.37; Fri, 08 Jul 2022 05:27:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@microchip.com header.s=mchp header.b=SjjzLQYe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238197AbiGHL5M (ORCPT + 99 others); Fri, 8 Jul 2022 07:57:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238194AbiGHL5L (ORCPT ); Fri, 8 Jul 2022 07:57:11 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC4D39A6B7; Fri, 8 Jul 2022 04:57:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657281430; x=1688817430; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CyBTxJhF4CejcV8FiE0ZwQp4QrBmvXQ9X9ymIPXP4U0=; b=SjjzLQYe7Xblh0GDjzIPal4fWvpj5UCkR/Qj4uy2HGQfQpshbotmmtPt gcT6ro7ih+1phslfvIQiiBiHOLrNrAcQ4NhEzGF3SP+IbV5E1xFCnQD6l DkQShF1qDrwRYzkSAUnW7SjMvP4ZfZ3GHad8uSrq0W3SqHMhhJL+Lyw6j tm3ukNzeapJaB5/7LYWbE7jIU9okQM2mTKw2AtVOGD2qy+tz7zW2AbRG5 CL9mzxodusWxMux/PlHgr/8W8lWc8n+gNAnKHNGDtECpC4U56Gc8LyDpm jRIb0MEWzwMfJwSyGErrX+lsc9ZSMh4z0Z5CmpZSnEgyo75w1gu8umsqA A==; X-IronPort-AV: E=Sophos;i="5.92,255,1650956400"; d="scan'208";a="163912214" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Jul 2022 04:57:09 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Jul 2022 04:57:06 -0700 Received: from kavya.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Jul 2022 04:57:03 -0700 From: Kavyasree Kotagiri To: , , , , , CC: , , , Subject: [PATCH v8 1/3] dt-bindings: mfd: Convert atmel-flexcom to json-schema Date: Fri, 8 Jul 2022 09:56:17 -0200 Message-ID: <20220708115619.254073-2-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708115619.254073-1-kavyasree.kotagiri@microchip.com> References: <20220708115619.254073-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the Atmel flexcom device tree bindings to json schema. Signed-off-by: Kavyasree Kotagiri --- v7 -> v8: - Added back patternProperties for child nodes. v6 -> v7: - Change filename to atmel,sama5d2-flexcom.yaml - Add #address-cells, #size-cells to flexcom node - Fixed warnings. v5 -> v6: - Removed spi node from example as suggested by Rob and also pattern properties(spi dt-bindings conversion to yaml patch is under review). Once that is accepted, I will add back spi example through new patch. v4 -> v5: - Fixed indentations. v3 -> v4: - Corrected format of enum used for compatible string. v2 -> v3: - used enum for compatible string. - changed irq flag to IRQ_TYPE_LEVEL_HIGH in example. - fixed dtschema errors. v1 -> v2: - Fix title. .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 92 +++++++++++++++++++ .../devicetree/bindings/mfd/atmel-flexcom.txt | 63 ------------- 2 files changed, 92 insertions(+), 63 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-flexcom.txt diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml new file mode 100644 index 000000000000..bfa7d340a198 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/atmel,sama5d2-flexcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Flexcom (Flexible Serial Communication Unit) + +maintainers: + - Kavyasree Kotagiri + +description: + The Atmel Flexcom is just a wrapper which embeds a SPI controller, + an I2C controller and an USART. Only one function can be used at a + time and is chosen at boot time according to the device tree. + +properties: + compatible: + enum: + - atmel,sama5d2-flexcom + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + description: + One range for the full I/O register region. (including USART, + TWI and SPI registers). + items: + maxItems: 3 + + atmel,flexcom-mode: + description: | + Specifies the flexcom mode as follows: + 1: USART + 2: SPI + 3: I2C. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + +patternProperties: + "^serial@[0-9a-f]+$": + type: object + description: + Child node describing USART. See atmel-usart.txt for details + of USART bindings. + + "^spi@[0-9a-f]+$": + type: object + description: + Child node describing SPI. See ../spi/spi_atmel.txt for details + of SPI bindings. + + "^i2c@[0-9a-f]+$": + $ref: ../i2c/atmel,at91sam-i2c.yaml + description: + Child node describing I2C. + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + - ranges + - atmel,flexcom-mode + +additionalProperties: false + +examples: + - | + #include + + flx0: flexcom@f8034000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8034000 0x200>; + clocks = <&flx0_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8034000 0x800>; + atmel,flexcom-mode = <2>; + }; +... diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt deleted file mode 100644 index 9d837535637b..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt +++ /dev/null @@ -1,63 +0,0 @@ -* Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit) - -The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C -controller and an USART. Only one function can be used at a time and is chosen -at boot time according to the device tree. - -Required properties: -- compatible: Should be "atmel,sama5d2-flexcom" -- reg: Should be the offset/length value for Flexcom dedicated - I/O registers (without USART, TWI or SPI registers). -- clocks: Should be the Flexcom peripheral clock from PMC. -- #address-cells: Should be <1> -- #size-cells: Should be <1> -- ranges: Should be one range for the full I/O register region - (including USART, TWI and SPI registers). -- atmel,flexcom-mode: Should be one of the following values: - - <1> for USART - - <2> for SPI - - <3> for I2C - -Required child: -A single available child device of type matching the "atmel,flexcom-mode" -property. - -The phandle provided by the clocks property of the child is the same as one for -the Flexcom parent. - -For other properties, please refer to the documentations of the respective -device: -- ../serial/atmel-usart.txt -- ../spi/spi_atmel.txt -- ../i2c/i2c-at91.txt - -Example: - -flexcom@f8034000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8034000 0x200>; - clocks = <&flx0_clk>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8034000 0x800>; - atmel,flexcom-mode = <2>; - - spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&flx0_clk>; - clock-names = "spi_clk"; - atmel,fifo-size = <32>; - - flash@0 { - compatible = "atmel,at25f512b"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; -}; -- 2.25.1