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Date:   Fri, 8 Jul 2022 18:01:55 -0500
From:   Bjorn Helgaas <helgaas@kernel.org>
To:     Christian Marangi <ansuelsmth@gmail.com>
Cc:     Stanimir Varbanov <svarbanov@mm-sol.com>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Konrad Dybcio <konrad.dybcio@somainline.org>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        Rob Herring <robh@kernel.org>,
        Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
        Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org,
        linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
        stable@vger.kernel.org
Subject: Re: [PATCH] PCI: qcom: Enable clocks only after PARF_PHY setup for
 rev 2.1.0
Message-ID: <20220708230155.GA388993@bhelgaas>
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In-Reply-To: <20220708222743.27019-1-ansuelsmth@gmail.com>
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On Sat, Jul 09, 2022 at 12:27:43AM +0200, Christian Marangi wrote:
> We currently enable clocks BEFORE we write to PARF_PHY_CTRL reg to
> enable clocks and resets. This case the driver to never set to a ready
> state with the error 'Phy link never came up'.
> 
> This in fact is caused by the phy clock getting enabled before setting
> the required bits in the PARF regs.
> 
> A workaround for this was set but with this new discovery we can drop
> the workaround and use a proper solution to the problem by just enabling
> the clock only AFTER the PARF_PHY_CTRL bit is set.
> 
> This correctly setup the pcie line and makes it usable even when a
> bootloader leave the pcie line to a underfined state.

Is "pcie" here a signal name?  Maybe this refers to the "PCIe link"?

> Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
> Cc: stable@vger.kernel.org # v5.4+
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

Thanks, I put this on
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git,
pci/ctrl/qcom-pending branch (head 47b4ec9d2e60).

Can you take a look and make sure I didn't mess up the conflict
resolution with the rest of the series?

> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 10 ++++------
>  1 file changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 2ea13750b492..da13a66ced14 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -337,8 +337,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
>  	reset_control_assert(res->ext_reset);
>  	reset_control_assert(res->phy_reset);
>  
> -	writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
> -
>  	ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
>  	if (ret < 0) {
>  		dev_err(dev, "cannot enable regulators\n");
> @@ -381,15 +379,15 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
>  		goto err_deassert_axi;
>  	}
>  
> -	ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
> -	if (ret)
> -		goto err_clks;
> -
>  	/* enable PCIe clocks and resets */
>  	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
>  	val &= ~BIT(0);
>  	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
>  
> +	ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
> +	if (ret)
> +		goto err_clks;
> +
>  	if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
>  	    of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
>  		writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
> -- 
> 2.36.1
>