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[2620:137:e000::1:20]) by mx.google.com with ESMTP id z7-20020a056402274700b0042e0cfdab0fsi1420134edd.6.2022.07.08.23.59.28; Sat, 09 Jul 2022 00:00:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b="ottRu/Pg"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229679AbiGIGAp (ORCPT + 99 others); Sat, 9 Jul 2022 02:00:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229634AbiGIGAd (ORCPT ); Sat, 9 Jul 2022 02:00:33 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCF728AEF6; Fri, 8 Jul 2022 23:00:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657346431; x=1688882431; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=nt30bBXYQxj3wIUD5YWrfgOK4r6dcgXbMH9U/4HHkbM=; b=ottRu/Pg7HU9ugdNWN9bIAT2KmcuCbzufXuvsu5bCZCAcSfHB/+PJE7a JOmn/fqSYavffc9B+L323G8Yv2/GFKw1qLjIWSyPNf0kUJ3WTcf4mgPMc QRZeJgXMSF0p87bmNNXJJ0kh9/mhzwbohkfuUlvVwERs7w3ZFR2gJbaHb s=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 08 Jul 2022 23:00:30 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2022 23:00:29 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 8 Jul 2022 23:00:29 -0700 Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 8 Jul 2022 23:00:24 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson CC: Jonathan Marek , Jordan Crouse , Matthias Kaehlcke , "Douglas Anderson" , Akhil P Oommen , Andy Gross , Krzysztof Kozlowski , Rob Herring , , Subject: [PATCH v2 5/7] arm64: dts: qcom: sc7280: Update gpu register list Date: Sat, 9 Jul 2022 11:29:33 +0530 Message-ID: <20220709112837.v2.5.I7291c830ace04fce07e6bd95a11de4ba91410f7b@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1657346375-1461-1-git-send-email-quic_akhilpo@quicinc.com> References: <1657346375-1461-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update gpu register array with gpucc memory region. Signed-off-by: Akhil P Oommen --- (no changes since v1) arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e66fc67..defdb25 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2228,10 +2228,12 @@ compatible = "qcom,adreno-635.0", "qcom,adreno"; reg = <0 0x03d00000 0 0x40000>, <0 0x03d9e000 0 0x1000>, - <0 0x03d61000 0 0x800>; + <0 0x03d61000 0 0x800>, + <0 0x03d90000 0 0x2000>; reg-names = "kgsl_3d0_reg_memory", "cx_mem", - "cx_dbgc"; + "cx_dbgc", + "gpucc"; interrupts = ; iommus = <&adreno_smmu 0 0x401>; operating-points-v2 = <&gpu_opp_table>; -- 2.7.4