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Message-ID: <ea64c33f-9fc5-7c24-a101-da5d605863e1@birger-koblitz.de>
Date:   Sat, 9 Jul 2022 18:11:41 +0200
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Subject: Re: [PATCH] MIPS: smp-mt: enable all hardware interrupts on second
 VPE
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To:     Sander Vanheule <sander@svanheule.net>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc:     Marc Zyngier <maz@kernel.org>,
        Aleksander Jan Bajkowski <olek2@wp.pl>,
        Hauke Mehrtens <hauke@hauke-m.de>, linux-mips@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <20220702190705.5319-1-olek2@wp.pl>
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 <20220707143930.GA14693@alpha.franken.de>
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From:   Birger Koblitz <git@birger-koblitz.de>
In-Reply-To: <468a2c8578d099eef0e0106fe273f73f5d70ef94.camel@svanheule.net>
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Hi,

On 7/7/22 17:12, Sander Vanheule wrote:
> On Thu, 2022-07-07 at 16:39 +0200, Thomas Bogendoerfer wrote:
>> On Thu, Jul 07, 2022 at 02:57:15PM +0200, Martin Blumenstingl wrote:

>> IMHO there is the problem, irq-mips-cpu.c can only do CPU irq operations
>> on the same CPU. I've checked MIPS MT specs and it's possible do
>> modify CP0 registers between VPEs. Using that needs changes in
>> irq-mips-cpu.c. But mabye that's not woth the effort as probably
>> all SMP cabable platforms have some multi processort capable
>> interrupt controller implemented.
Not sure I can be of much help. That the patch works on the RTL SoCs is 
mostly empirical and was found in the vendor code.

My understanding from the MIPS documentation is that it is not specified 
what happens when a multi VPE capable IRQ controller triggers CPU 
interrupts: if multiple VPEs are possible targets, then it is not 
defined whether one of them gets them (and which one), multiple, or all. 
So trying to control what happens between VPEs is probably SoC-dependent 
functionality.

Cheers,
   Birger