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From:   Roman Stratiienko <r.stratiienko@gmail.com>
To:     samuel@sholland.org
Cc:     mturquette@baylibre.com, sboyd@kernel.org, mripard@kernel.org,
        wens@csie.org, jernej.skrabec@gmail.com, linux-clk@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev,
        linux-kernel@vger.kernel.org,
        Roman Stratiienko <r.stratiienko@gmail.com>
Subject: [RFC] ccu-sun50i-h6: Bump-up DDR0 PLL to 1800MHz
Date:   Sun, 10 Jul 2022 20:52:14 +0300
Message-Id: <20220710175214.544748-1-r.stratiienko@gmail.com>
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While debugging complex animated composition cases  I noticed a glitch
which as it turned-out eventually was caused by lack of memory bandwidth.

I can't find a DRAMC manual to check what input frequency must be
supplied to avoid exceeding the 800MHz LPDDR3 which is installed on
my orangepi3 board. But the system is running stable so far.

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
---
 drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index 750368a86b8b6..abdde80307993 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -1203,6 +1203,17 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev)
 	val &= ~GENMASK(3, 0);
 	writel(val, reg + gpu_clk.common.reg);
 
+	/*
+	 * Increase DDR0 PLL from 1488(default) to 1800MHz.
+	 * (DE3.0 require higher memory bandwidth while displaying
+	 * complex composition at 1920x1080@60FPS)
+	 */
+
+	val = readl(reg + SUN50I_H6_PLL_DDR0_REG);
+	val &= ~GENMASK(15, 0);
+	val |= 74 << 8;
+	writel(val, reg + SUN50I_H6_PLL_DDR0_REG);
+
 	/* Enable the lock bits on all PLLs */
 	for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
 		val = readl(reg + pll_regs[i]);
-- 
2.34.1