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Message-ID: <32cffa34-1088-5e25-3051-192e3049908f@quicinc.com>
Date:   Mon, 11 Jul 2022 13:24:10 +0530
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Subject: Re: [PATCH v2] arm64: dts: qcom: sc7280: Move wcd specific pin conf
 to common file
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To:     Stephen Boyd <swboyd@chromium.org>, <agross@kernel.org>,
        <bjorn.andersson@linaro.org>, <devicetree@vger.kernel.org>,
        <dianders@chromium.org>, <judyhsiao@chromium.org>,
        <linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <quic_rohkumar@quicinc.com>, <robh+dt@kernel.org>,
        <srinivas.kandagatla@linaro.org>
References: <1657197381-1271-1-git-send-email-quic_srivasam@quicinc.com>
 <CAE-0n53X8yyWr+Q+3RpciCeZcW+t+jgZs3eqNF9O8hJcw0cq0Q@mail.gmail.com>
From:   Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Organization: Qualcomm
In-Reply-To: <CAE-0n53X8yyWr+Q+3RpciCeZcW+t+jgZs3eqNF9O8hJcw0cq0Q@mail.gmail.com>
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On 7/8/2022 11:29 PM, Stephen Boyd wrote:
Thanks for your time Stephen!!!
> Quoting Srinivasa Rao Mandadapu (2022-07-07 05:36:21)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi
>> index 32a1e78..859faaa 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi
>> @@ -5,6 +5,70 @@
>>    * Copyright (c) 2022, The Linux Foundation. All rights reserved.
>>    */
>>
>> +/* PINCTRL */
>> +
>> +&lpass_dmic01_clk {
>> +       drive-strength = <8>;
>> +       bias-disable;
>> +};
>> +
>> +&lpass_dmic01_clk_sleep {
>> +       drive-strength = <2>;
>> +};
>> +
>> +&lpass_dmic01_data {
>> +       bias-pull-down;
>> +};
>> +
>> +&lpass_dmic23_clk {
>> +       drive-strength = <8>;
>> +       bias-disable;
>> +};
>> +
>> +&lpass_dmic23_clk_sleep {
>> +       drive-strength = <2>;
>> +};
>> +
>> +&lpass_dmic23_data {
>> +       bias-pull-down;
>> +};
>> +
>> +&lpass_rx_swr_clk {
>> +       drive-strength = <2>;
>> +       slew-rate = <1>;
>> +       bias-disable;
>> +};
>> +
>> +&lpass_rx_swr_clk_sleep {
>> +       bias-pull-down;
>> +};
>> +
>> +&lpass_rx_swr_data {
>> +       drive-strength = <2>;
> I suspect this was discussed before, but why do we need to modify drive
> strengths on pins that aren't in output mode? I assume either rx_swr or
> tx_swr is unidirectional.

Actually this patch is just reorganization only. didn't do any 
modification of already reviewed patches.

Will test without drive strength again and post a fix patch post this 
patch accepted if required.

>
>> +       slew-rate = <1>;
>> +       bias-bus-hold;
>> +};
>> +
>> +&lpass_rx_swr_data_sleep {
>> +       bias-pull-down;
>> +};
>> +
>> +&lpass_tx_swr_clk {
>> +       drive-strength = <2>;
>> +       slew-rate = <1>;
>> +       bias-disable;
>> +};
>> +
>> +&lpass_tx_swr_clk_sleep {
>> +       bias-pull-down;
>> +};
>> +
>> +&lpass_tx_swr_data {
>> +       drive-strength = <2>;
>> +       slew-rate = <1>;
>> +       bias-bus-hold;
>> +};
>> +
>>   &mi2s1_data0 {
>>          drive-strength = <6>;
>>          bias-disable;