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Date:   Mon, 11 Jul 2022 14:47:54 +0200
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Subject: Re: [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI
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To:     Mark Brown <broonie@kernel.org>,
        Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
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From:   Michal Simek <michal.simek@xilinx.com>
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Hi Mark,

On 6/9/22 13:54, Mark Brown wrote:
> On Mon, Jun 06, 2022 at 04:56:06PM +0530, Amit Kumar Mahapatra wrote:
> 
>> ---
>>   drivers/spi/spi-zynqmp-gqspi.c | 30 ++++++++++++++++++++++++++----
>>   drivers/spi/spi.c              | 10 +++++++---
>>   include/linux/spi/spi.h        | 10 +++++++++-
>>   3 files changed, 42 insertions(+), 8 deletions(-)
> 
> Please split the core and driver support into separate patches, they are
> separate things.
> 
>> --- a/drivers/spi/spi.c
>> +++ b/drivers/spi/spi.c
>> @@ -2082,6 +2082,8 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
>>   {
>>   	u32 value;
>>   	int rc;
>> +	u32 cs[SPI_CS_CNT_MAX];
>> +	u8 idx;
>>   
>>   	/* Mode (clock phase/polarity/etc.) */
>>   	if (of_property_read_bool(nc, "spi-cpha"))
> 
> This is changing the DT binding but doesn't have any updates to the
> binding document.  The binding code also doesn't validate that we don't
> have too many chip selects.

I would like to better understand your request here in connection to change in 
the binding code for validation.
What exactly do you want to validate?
That child reg property is not bigger than num-cs in controller node?

Adding also Krzysztof because I was talking to him over IRC about this.

Thanks,
Michal