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[2620:137:e000::1:20]) by mx.google.com with ESMTP id q141-20020a632a93000000b00412a8407906si10169886pgq.626.2022.07.11.08.24.44; Mon, 11 Jul 2022 08:24:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229477AbiGKOhC (ORCPT + 99 others); Mon, 11 Jul 2022 10:37:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229795AbiGKOhA (ORCPT ); Mon, 11 Jul 2022 10:37:00 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B159765D7C for ; Mon, 11 Jul 2022 07:36:59 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C4F4B1596; Mon, 11 Jul 2022 07:36:59 -0700 (PDT) Received: from bogus (unknown [10.57.39.193]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E1FCB3F70D; Mon, 11 Jul 2022 07:36:53 -0700 (PDT) Date: Mon, 11 Jul 2022 15:35:42 +0100 From: Sudeep Holla To: Conor Dooley Cc: Paul Walmsley , Palmer Dabbelt , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , Sudeep Holla , Greg Kroah-Hartman , "Rafael J . Wysocki" , Daire McNamara , Conor Dooley , Niklas Cassel , Damien Le Moal , Geert Uytterhoeven , Zong Li , Emil Renner Berthing , Jonas Hahnfeld , Guo Ren , Anup Patel , Atish Patra , Heiko Stuebner , Philipp Tomsich , Rob Herring , Marc Zyngier , Viresh Kumar , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Brice Goglin Subject: Re: [PATCH v3 1/2] arm64: topology: move store_cpu_topology() to shared code Message-ID: <20220711143542.nlq6a5nuh4nouomo@bogus> References: <20220709152354.2856586-1-mail@conchuod.ie> <20220709152354.2856586-2-mail@conchuod.ie> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220709152354.2856586-2-mail@conchuod.ie> X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Jul 09, 2022 at 04:23:54PM +0100, Conor Dooley wrote: > From: Conor Dooley > > arm64's method of defining a default cpu topology requires only minimal > changes to apply to RISC-V also. The current arm64 implementation exits > early in a uniprocessor configuration by reading MPIDR & claiming that > uniprocessor can rely on the default values. > > This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64: > topology: Stop using MPIDR for topology information")', because the > current code just assigns default values for multiprocessor systems. > > With the MPIDR references removed, store_cpu_topolgy() can be moved to > the common arch_topology code. > Looks good. FWIW, Reviewed-by: Sudeep Holla > CC: stable@vger.kernel.org However, while I understand the reason why this is needed in stable trees for RISC-V, I am not sure if we want this for stable tree at-least on arm64. I leave that part to Greg and Will. -- Regards, Sudeep