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Mon, 11 Jul 2022 16:45:20 +0000 Received: from MN2PR12MB4333.namprd12.prod.outlook.com ([fe80::69d7:4030:98ab:3593]) by MN2PR12MB4333.namprd12.prod.outlook.com ([fe80::69d7:4030:98ab:3593%5]) with mapi id 15.20.5417.026; Mon, 11 Jul 2022 16:45:20 +0000 From: "Mehta, Piyush" To: Peter Chen , Piyush Mehta CC: "gregkh@linuxfoundation.org" , "michal.simek@xilinx.com" , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "git@xilinx.com" , "sivadur@xilinx.com" , "radheys@xilinx.com" Subject: RE: [RFC PATCH] usb: chipidea: Add support for VBUS control with PHY Thread-Topic: [RFC PATCH] usb: chipidea: Add support for VBUS control with PHY Thread-Index: AQHYb2cEXoSLgZPquEiCXVJMPsCDdq1sCocAgA2hGAA= Date: Mon, 11 Jul 2022 16:45:20 +0000 Message-ID: References: <20220524120802.9394-1-piyush.mehta@xilinx.com> <20220703003434.GA1382015@Peter> In-Reply-To: <20220703003434.GA1382015@Peter> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4333.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9b182ff7-00fe-4541-ace7-08da635cbe06 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Jul 2022 16:45:20.1971 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: uEkMOQE7CAulwFUNs+iEcYiJaOrrem59nkpwiimfBlNCE2JGOm0whl8/DjaRBX6O X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB4694 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Peter, Thanks for the review. Yes, we are supporting OTG feature and have used OTG FSM platform. Regards, Piyush Mehta=20 > -----Original Message----- > From: Peter Chen > Sent: Sunday, July 3, 2022 6:05 AM > To: Piyush Mehta > Cc: gregkh@linuxfoundation.org; michal.simek@xilinx.com; linux- > usb@vger.kernel.org; linux-kernel@vger.kernel.org; git@xilinx.com; > sivadur@xilinx.com; radheys@xilinx.com > Subject: Re: [RFC PATCH] usb: chipidea: Add support for VBUS control with > PHY >=20 > CAUTION: This message has originated from an External Source. Please use > proper judgment and caution when opening attachments, clicking links, or > responding to this email. >=20 >=20 > On 22-05-24 17:38:02, Piyush Mehta wrote: > > Some platforms make use of VBUS control over PHY which means > > controller driver has to access PHY registers to turn on/off VBUS > > line.This patch adds support for such platforms in chipidea. > > > > Flag 'CI_HDRC_PHY_VBUS_CONTROL' added to support VBus control > feature. > > > > Signed-off-by: Piyush Mehta > > --- > > We have created this patch as RFC, as I introduced a new flag > > (CI_HDRC_PHY_VBUS_CONTROL) and would like to get comment if it's the > > proper way to check for VBus support for zynq. > > --- > > drivers/usb/chipidea/ci_hdrc_usb2.c | 1 + > > drivers/usb/chipidea/host.c | 7 +++++++ > > drivers/usb/chipidea/otg_fsm.c | 7 +++++++ > > include/linux/usb/chipidea.h | 1 + > > 4 files changed, 16 insertions(+) > > > > diff --git a/drivers/usb/chipidea/ci_hdrc_usb2.c > > b/drivers/usb/chipidea/ci_hdrc_usb2.c > > index 89e1d82..dc86b12 100644 > > --- a/drivers/usb/chipidea/ci_hdrc_usb2.c > > +++ b/drivers/usb/chipidea/ci_hdrc_usb2.c > > @@ -30,6 +30,7 @@ static const struct ci_hdrc_platform_data > > ci_default_pdata =3D { > > > > static const struct ci_hdrc_platform_data ci_zynq_pdata =3D { > > .capoffset =3D DEF_CAPOFFSET, > > + .flags =3D CI_HDRC_PHY_VBUS_CONTROL, > > }; > > > > static const struct ci_hdrc_platform_data ci_zevio_pdata =3D { diff > > --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c > > index bdc3885..bc3634a 100644 > > --- a/drivers/usb/chipidea/host.c > > +++ b/drivers/usb/chipidea/host.c > > @@ -63,6 +63,13 @@ static int ehci_ci_portpower(struct usb_hcd *hcd, in= t > portnum, bool enable) > > priv->enabled =3D enable; > > } > > > > + if (ci->platdata->flags & CI_HDRC_PHY_VBUS_CONTROL) { > > + if (enable) > > + usb_phy_vbus_on(ci->usb_phy); > > + else > > + usb_phy_vbus_off(ci->usb_phy); > > + } > > + > > if (enable && (ci->platdata->phy_mode =3D=3D > USBPHY_INTERFACE_MODE_HSIC)) { > > /* > > * Marvell 28nm HSIC PHY requires forcing the port to HS = mode. > > diff --git a/drivers/usb/chipidea/otg_fsm.c > > b/drivers/usb/chipidea/otg_fsm.c index 6ed4b00..5ed9164 100644 > > --- a/drivers/usb/chipidea/otg_fsm.c > > +++ b/drivers/usb/chipidea/otg_fsm.c > > @@ -471,6 +471,10 @@ static void ci_otg_drv_vbus(struct otg_fsm *fsm, > int on) > > return; > > } > > } > > + > > + if (ci->platdata->flags & CI_HDRC_PHY_VBUS_CONTROL) > > + usb_phy_vbus_on(ci->usb_phy); > > + > > /* Disable data pulse irq */ > > hw_write_otgsc(ci, OTGSC_DPIE, 0); > > > > @@ -480,6 +484,9 @@ static void ci_otg_drv_vbus(struct otg_fsm *fsm, in= t > on) > > if (ci->platdata->reg_vbus) > > regulator_disable(ci->platdata->reg_vbus); > > > > + if (ci->platdata->flags & CI_HDRC_PHY_VBUS_CONTROL) > > + usb_phy_vbus_off(ci->usb_phy); > > + >=20 > Have your platform used OTG FSM? If not used, do not need to change it. > Otherwise, it is okay for me. >=20 > Peter >=20 > > fsm->a_bus_drop =3D 1; > > fsm->a_bus_req =3D 0; > > } > > diff --git a/include/linux/usb/chipidea.h > > b/include/linux/usb/chipidea.h index edf3342..ee38835 100644 > > --- a/include/linux/usb/chipidea.h > > +++ b/include/linux/usb/chipidea.h > > @@ -62,6 +62,7 @@ struct ci_hdrc_platform_data { #define > > CI_HDRC_REQUIRES_ALIGNED_DMA BIT(13) > > #define CI_HDRC_IMX_IS_HSIC BIT(14) > > #define CI_HDRC_PMQOS BIT(15) > > +#define CI_HDRC_PHY_VBUS_CONTROL BIT(16) > > enum usb_dr_mode dr_mode; > > #define CI_HDRC_CONTROLLER_RESET_EVENT 0 > > #define CI_HDRC_CONTROLLER_STOPPED_EVENT 1 > > -- > > 2.7.4 > > >=20 > -- >=20 > Thanks, > Peter Chen