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[193.116.203.247]) by smtp.gmail.com with ESMTPSA id 200-20020a6219d1000000b00528d7d27211sm5420305pfz.178.2022.07.11.17.06.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 17:06:58 -0700 (PDT) Date: Tue, 12 Jul 2022 10:06:52 +1000 From: Nicholas Piggin Subject: Re: [PATCH 02/13] locking/qspinlock: inline mcs_spinlock functions into qspinlock To: Peter Zijlstra Cc: Boqun Feng , linux-kernel@vger.kernel.org, Waiman Long , Ingo Molnar , Will Deacon References: <20220704143820.3071004-1-npiggin@gmail.com> <20220704143820.3071004-3-npiggin@gmail.com> In-Reply-To: MIME-Version: 1.0 Message-Id: <1657584250.pjnraozr5g.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Excerpts from Peter Zijlstra's message of July 6, 2022 2:57 am: > On Tue, Jul 05, 2022 at 12:38:09AM +1000, Nicholas Piggin wrote: >> qspinlock uses mcs_spinlock for the struct type (.next, .locked, and the >> misplaced .count), and arch_mcs_spin_{un}lock_contended(). These can be >> trivially inlined into qspinlock, and the unused mcs_spinlock code >> removed. >>=20 >> Signed-off-by: Nicholas Piggin >> --- >=20 >> arch/arm/include/asm/mcs_spinlock.h | 24 ------ >=20 >> --- a/arch/arm/include/asm/mcs_spinlock.h >> +++ /dev/null >> @@ -1,24 +0,0 @@ >> -/* SPDX-License-Identifier: GPL-2.0 */ >> -#ifndef __ASM_MCS_LOCK_H >> -#define __ASM_MCS_LOCK_H >> - >> -#ifdef CONFIG_SMP >> -#include >> - >> -/* MCS spin-locking. */ >> -#define arch_mcs_spin_lock_contended(lock) \ >> -do { \ >> - /* Ensure prior stores are observed before we enter wfe. */ \ >> - smp_mb(); \ >> - while (!(smp_load_acquire(lock))) \ >> - wfe(); \ >> -} while (0) \ >> - >> -#define arch_mcs_spin_unlock_contended(lock) \ >> -do { \ >> - smp_store_release(lock, 1); \ >> - dsb_sev(); \ >> -} while (0) >> - >> -#endif /* CONFIG_SMP */ >> -#endif /* __ASM_MCS_LOCK_H */ >=20 >> @@ -475,7 +476,8 @@ void queued_spin_lock_slowpath(struct qspinlock *loc= k, u32 val) >> WRITE_ONCE(prev->next, node); >> =20 >> pv_wait_node(node, prev); >> - arch_mcs_spin_lock_contended(&node->locked); >> + /* Wait for mcs node lock to be released */ >> + smp_cond_load_acquire(&node->locked, VAL); >> =20 >> /* >> * While waiting for the MCS lock, the next pointer may have >> @@ -554,7 +556,7 @@ void queued_spin_lock_slowpath(struct qspinlock *loc= k, u32 val) >> if (!next) >> next =3D smp_cond_load_relaxed(&node->next, (VAL)); >> =20 >> - arch_mcs_spin_unlock_contended(&next->locked); >> + smp_store_release(&next->locked, 1); /* unlock the mcs node lock */ >=20 > These are not equivalent. Now it so happens that ARM doesn't use > qspinlock and the other mcs lock users are gone by now, but something > like this should at least have been called out in the Changelog I think. >=20 Yeah I could mention it in the changelog, I just didn't because it is practically equivalent. Thanks, Nick