Received: by 2002:ad5:4acb:0:0:0:0:0 with SMTP id n11csp4209imw; Tue, 12 Jul 2022 13:22:05 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vVhO6lClEAuA1YWLK3XHq3U5mw7s1FLVUvpRYS5rH0rkyYJNqHnPdD2AJapT1F/jL3ZvaL X-Received: by 2002:a17:907:8a04:b0:72b:9173:2fef with SMTP id sc4-20020a1709078a0400b0072b91732fefmr1556954ejc.346.1657657325415; Tue, 12 Jul 2022 13:22:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657657325; cv=none; d=google.com; s=arc-20160816; b=vlm3qoMos8PqUxQl/WamOvXoozd8Pk29QM4oIfHBAjxU1FCGXikSw7puImcMstXhKA +0bw6+SOpGpkRX3o8qA6ig2bHHLB7eO3l2p4z4SgPRgwjryy6aHnb6VdYz0iDZThnVOK anrfJDtrknC7bL/QIZREJW1gTAz/U9JCgm/eyxhWcCBIKHHwMvO+mXG62J3E5rgke2aM 5KrsWb3B/NipwOJZmVIn8F7V/nrsHQx4UG5l8f1t66+DrC2zGP+mqP4/bfpW27JZfnN/ Q4GZHMdqkU2ZTGua0vsj4YpoUtxEygbKyxCU6DilKDge+33qPGo+hv/v3GTrD1jYRr1d yVKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nNTZ6meKaOy6CIbnMvISXt5PCAHI1rUsoUiWqYaBrpU=; b=quu9klZ47MuFaqh+6nFNiBGhs1dKa75VHKpqKJjnn/9C4qTnQhiansduJrVmAdISd0 /+aLItcdFg6Og1wnMjbmLJx+rbrmYHX5hKhsKSANxGaPoZJcYIxdOFEUUSPVFcQXSEkX 7gZqSq93ljUTVgV5XM2ZWDfShhwonqsSHpxhcr5apNK7k6q4EW7W+H40yiQ3eOz1ojWd WodoKg9AgHYc+0vMex+BiBdKQrBPO3QHZgw/HPQNAfyn7DT9gXiLAtKICZddazCZn9lj ojFhrXM9akqOM0CgyxPGruZMotD2dvuUS8shZX/AdcGu9YO0s80ChBKgfvesCWD1FFZY iB0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=QgUY620m; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id go31-20020a1709070d9f00b0072b3cd7beb8si19090863ejc.938.2022.07.12.13.21.40; Tue, 12 Jul 2022 13:22:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=QgUY620m; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233044AbiGLTwv (ORCPT + 99 others); Tue, 12 Jul 2022 15:52:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233311AbiGLTwc (ORCPT ); Tue, 12 Jul 2022 15:52:32 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 455D2B38D8; Tue, 12 Jul 2022 12:46:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657655217; x=1689191217; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o6Smb2LVrKinxr1kedwUxtMmyszMdP7k3W+zKSv/R04=; b=QgUY620m5q8A226FaopbPUrd3+VkirkxaN93Zap8hHOB6wVxzmkUsafR Ys9BrHggpOqFee0eOBkMLjoAy9duaKUwXeZWBs60qPG6MFuOhVwS41cuu /EniF1EVAFOonOWWxGeT9YrnRd7MrLCJoqeBP1p2GeD0zjmwoNz8FBfic nyUMfJO1QGJ+Sw9p9eF6srxA18ZF76V7INiNoBuzjStoSz5BURtmE8ZPt SIKBsZjhZeveS1hT2XuFHZ6VlBuPOhNeKp+KewYX2J3x8TTiRX3PYhx5I 2s+rJIlMmEe/4vUA/ZmwxaL5+4lX52w3uu5TqNGsBg68ORPLzziMldHjp w==; X-IronPort-AV: E=Sophos;i="5.92,266,1650956400"; d="scan'208";a="167525930" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Jul 2022 12:46:55 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 12 Jul 2022 12:46:55 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 12 Jul 2022 12:46:52 -0700 From: Horatiu Vultur To: , CC: , , , , , , , , Horatiu Vultur Subject: [PATCH v4 2/2] pinctrl: ocelot: Fix pincfg Date: Tue, 12 Jul 2022 21:50:43 +0200 Message-ID: <20220712195043.3842081-3-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220712195043.3842081-1-horatiu.vultur@microchip.com> References: <20220712195043.3842081-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Spam-Status: No, score=-5.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The blamed commit changed to use regmaps instead of __iomem. But it didn't update the register offsets to be at word offset, so it uses byte offset. Another issue with the same commit is that it has a limit of 32 registers which is incorrect. The sparx5 has 64 while lan966x has 77. Fixes: 076d9e71bcf8 ("pinctrl: ocelot: convert pinctrl to regmap") Signed-off-by: Horatiu Vultur --- drivers/pinctrl/pinctrl-ocelot.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 873bba245522..c5a9f87f0c49 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -1334,7 +1334,9 @@ static int ocelot_hw_get_value(struct ocelot_pinctrl *info, const struct ocelot_pincfg_data *opd = info->pincfg_data; u32 regcfg; - ret = regmap_read(info->pincfg, pin, ®cfg); + ret = regmap_read(info->pincfg, + pin * regmap_get_reg_stride(info->pincfg), + ®cfg); if (ret) return ret; @@ -1366,14 +1368,18 @@ static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, u32 val; int ret; - ret = regmap_read(info->pincfg, regaddr, &val); + ret = regmap_read(info->pincfg, + regaddr * regmap_get_reg_stride(info->pincfg), + &val); if (ret) return ret; val &= ~clrbits; val |= setbits; - ret = regmap_write(info->pincfg, regaddr, val); + ret = regmap_write(info->pincfg, + regaddr * regmap_get_reg_stride(info->pincfg), + val); return ret; } @@ -1932,7 +1938,8 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = { {}, }; -static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) +static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev, + const struct ocelot_pinctrl *info) { void __iomem *base; @@ -1940,7 +1947,7 @@ static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) .reg_bits = 32, .val_bits = 32, .reg_stride = 4, - .max_register = 32, + .max_register = info->desc->npins * 4, .name = "pincfg", }; @@ -2008,7 +2015,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) /* Pinconf registers */ if (info->desc->confops) { - pincfg = ocelot_pinctrl_create_pincfg(pdev); + pincfg = ocelot_pinctrl_create_pincfg(pdev, info); if (IS_ERR(pincfg)) dev_dbg(dev, "Failed to create pincfg regmap\n"); else -- 2.33.0