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Date:   Tue, 12 Jul 2022 20:22:52 +0000
To:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        =?utf-8?Q?Tam=C3=A1s_Sz=C5=B1cs?= <tszucs@protonmail.ch>,
        Dong Aisheng <aisheng.dong@nxp.com>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
From:   =?utf-8?Q?Tam=C3=A1s_Sz=C5=B1cs?= <tszucs@protonmail.ch>
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Subject: [PATCH 1/2] arm64: dts: imx8qm-mek: mux and hook up GPIOs related to SD1
Message-ID: <20220712202211.8592-1-tszucs@protonmail.ch>
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Add pinctrl node grouping USDHC1_DATA6, USDHC1_DATA7 and USDHC1_RESET_B and=
 use
them as Write Protect and Card Detect for usdhc2 and regulator enable for
SD1_SPWR respectively.

Fixes: 307fd14d4b14 ("arm64: dts: imx: add imx8qm mek support")

Signed-off-by: Tam=C3=A1s Sz=C5=B1cs <tszucs@protonmail.ch>
---
 arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot=
/dts/freescale/imx8qm-mek.dts
index ce9d3f0b98fc..19b60efe3639 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -32,7 +32,7 @@ reg_usdhc2_vmmc: usdhc2-vmmc {
 =09=09regulator-name =3D "SD1_SPWR";
 =09=09regulator-min-microvolt =3D <3000000>;
 =09=09regulator-max-microvolt =3D <3000000>;
-=09=09gpio =3D <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
+=09=09gpio =3D <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
 =09=09enable-active-high;
 =09};
 };
@@ -79,11 +79,11 @@ &usdhc1 {

 &usdhc2 {
 =09pinctrl-names =3D "default";
-=09pinctrl-0 =3D <&pinctrl_usdhc2>;
+=09pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 =09bus-width =3D <4>;
 =09vmmc-supply =3D <&reg_usdhc2_vmmc>;
-=09cd-gpios =3D <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
-=09wp-gpios =3D <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
+=09cd-gpios =3D <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
+=09wp-gpios =3D <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
 =09status =3D "okay";
 };

@@ -141,4 +141,12 @@ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3=09=09=090x000000=
21
 =09=09=09IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT=09=090x00000021
 =09=09>;
 =09};
+
+=09pinctrl_usdhc2_gpio: usdhc2grpgpio {
+=09=09fsl,pins =3D <
+=09=09=09IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21=09=09=090x00000021
+=09=09=09IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22=09=09=090x00000021
+=09=09=09IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07=09=09=090x00000021
+=09=09>;
+=09};
 };
--
2.30.2