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From:   Johan Hovold <johan+linaro@kernel.org>
To:     Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Felipe Balbi <balbi@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>
Cc:     Andy Gross <agross@kernel.org>,
        Konrad Dybcio <konrad.dybcio@somainline.org>,
        Wesley Cheng <quic_wcheng@quicinc.com>,
        linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Johan Hovold <johan+linaro@kernel.org>
Subject: [PATCH 4/7] arm64: dts: qcom: sc8280xp: fix USB clock order
Date:   Wed, 13 Jul 2022 15:13:37 +0200
Message-Id: <20220713131340.29401-5-johan+linaro@kernel.org>
In-Reply-To: <20220713131340.29401-1-johan+linaro@kernel.org>
References: <20220713131340.29401-1-johan+linaro@kernel.org>
MIME-Version: 1.0
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Precedence: bulk

Fix the USB controller clock order and naming so that they match the
devicetree binding.

Note that the driver currently simply enables all clocks in the order
that they are specified in the devicetree. Reordering the clocks as per
the binding means that the only explicit ordering constraint found in
the vendor driver, that cfg_noc should be enabled before the core_clk,
is now honoured.

Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 285a9828c250..45cc7d714fd2 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1855,16 +1855,16 @@ usb_0: usb@a6f8800 {
 			#size-cells = <2>;
 			ranges;
 
-			clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
-				 <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
 				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
-				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
 				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
 				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
 				 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
 				 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
 				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
-			clock-names = "core", "iface", "bus_aggr", "utmi", "sleep",
+			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
 				      "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
 
 			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
@@ -1905,16 +1905,16 @@ usb_1: usb@a8f8800 {
 			#size-cells = <2>;
 			ranges;
 
-			clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
-				 <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
 				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
-				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
 				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
+				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
 				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
 				 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
 				 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
 				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
-			clock-names = "core", "iface", "bus_aggr", "utmi", "sleep",
+			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
 				      "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
 
 			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
-- 
2.35.1