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Message-ID: <d8bc7a14-a9c5-4d34-997a-48a8d27c5edd@linaro.org>
Date:   Wed, 13 Jul 2022 16:28:57 +0200
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Subject: Re: [PATCH v1 2/2] pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO
 driver
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To:     Tomer Maimon <tmaimon77@gmail.com>
Cc:     Avi Fishman <avifishman70@gmail.com>,
        Tali Perry <tali.perry1@gmail.com>,
        Joel Stanley <joel@jms.id.au>,
        Patrick Venture <venture@google.com>,
        Nancy Yuen <yuenn@google.com>,
        Benjamin Fair <benjaminfair@google.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        =?UTF-8?Q?Jonathan_Neusch=c3=a4fer?= <j.neuschaefer@gmx.net>,
        zhengbin13@huawei.com, OpenBMC Maillist <openbmc@lists.ozlabs.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        devicetree <devicetree@vger.kernel.org>
References: <20220710102110.39748-1-tmaimon77@gmail.com>
 <20220710102110.39748-3-tmaimon77@gmail.com>
 <95d12b72-be9d-5503-c4ea-801303bb7776@linaro.org>
 <CAP6Zq1geFJsKrdQEN5Vqjw6e8bsiArDe1tzJ-jkQm-2XT-0KyQ@mail.gmail.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <CAP6Zq1geFJsKrdQEN5Vqjw6e8bsiArDe1tzJ-jkQm-2XT-0KyQ@mail.gmail.com>
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On 13/07/2022 15:35, Tomer Maimon wrote:

>>> +static int npcm8xx_pinctrl_probe(struct platform_device *pdev)
>>> +{
>>> +     struct npcm8xx_pinctrl *pctrl;
>>> +     int ret;
>>> +
>>> +     pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
>>> +     if (!pctrl)
>>> +             return -ENOMEM;
>>> +
>>> +     pctrl->dev = &pdev->dev;
>>> +     dev_set_drvdata(&pdev->dev, pctrl);
>>> +
>>> +     pctrl->gcr_regmap =
>>> +             syscon_regmap_lookup_by_compatible("nuvoton,npcm845-gcr");
>>
>> No. Use property. By this patchset, I would expect that you learnt from
>> previous mistakes around this. Why repeating the same trouble second time?
> You suggest to use phandle property like nuvoton,sysgcr even that the
> NPCM8XX pin controller driver is used only NPCM8XX SoC, so the only
> GCR node in the NPCM8XX SoC is nuvoton,npcm845-gcr?

Yes. The previous case (reset driver, AFAIR) was also about driver used
only in one SoC, wasn't it?

Best regards,
Krzysztof