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From:   Vitaly Kuznetsov <vkuznets@redhat.com>
To:     kvm@vger.kernel.org, Paolo Bonzini <pbonzini@redhat.com>,
        Sean Christopherson <seanjc@google.com>
Cc:     Wanpeng Li <wanpengli@tencent.com>,
        Jim Mattson <jmattson@google.com>,
        Maxim Levitsky <mlevitsk@redhat.com>,
        linux-kernel@vger.kernel.org
Subject: [PATCH 0/3] KVM: x86: Hyper-V invariant TSC control feature
Date:   Wed, 13 Jul 2022 17:05:29 +0200
Message-Id: <20220713150532.1012466-1-vkuznets@redhat.com>
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Normally, genuine Hyper-V doesn't expose architectural invariant TSC
(CPUID.80000007H:EDX[8]) to its guests by default. A special PV MSR
(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x40000118) and corresponding CPUID
feature bit (CPUID.0x40000003.EAX[15]) were introduced. When bit 0 of the
PV MSR is set, invariant TSC bit starts to show up in CPUID. When the 
feature is exposed to Hyper-V guests, reenlightenment becomes unneeded.

Note: strictly speaking, KVM doesn't have to have the feature as exposing
raw invariant TSC bit (CPUID.80000007H:EDX[8]) also seems to work for
modern Windows versions. The feature is, however, tiny and straitforward
and gives additional flexibility so why not.

Vitaly Kuznetsov (3):
  KVM: x86: Hyper-V invariant TSC control
  KVM: selftests: Fix wrmsr_safe()
  KVM: selftests: Test Hyper-V invariant TSC control

 arch/x86/include/asm/kvm_host.h               |  1 +
 arch/x86/kvm/cpuid.c                          |  7 ++
 arch/x86/kvm/hyperv.c                         | 19 +++++
 arch/x86/kvm/hyperv.h                         | 15 ++++
 arch/x86/kvm/x86.c                            |  4 +-
 .../selftests/kvm/include/x86_64/processor.h  |  2 +-
 .../selftests/kvm/x86_64/hyperv_features.c    | 73 ++++++++++++++++++-
 7 files changed, 115 insertions(+), 6 deletions(-)

-- 
2.35.3