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Date:   Thu, 14 Jul 2022 14:06:42 +0200
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Subject: Re: [PATCH v2] memory: dfl-emif: Update the dfl emif driver support
 revision 1
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To:     Tianfei Zhang <tianfei.zhang@intel.com>, ssantosh@kernel.org
Cc:     trix@redhat.com, yilun.xu@intel.com, russell.h.weight@intel.com,
        linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org,
        matthew.gerlach@linux.intel.com,
        Debarati Biswas <debaratix.biswas@intel.com>
References: <20220713130355.196115-1-tianfei.zhang@intel.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <20220713130355.196115-1-tianfei.zhang@intel.com>
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On 13/07/2022 15:03, Tianfei Zhang wrote:
> From: Debarati Biswas <debaratix.biswas@intel.com>
> 
> The next generation (revision 1) of the DFL EMIF feature device requires
> support for more than 4 memory banks. It does not support the selective
> clearing of memory banks. A capability register replaces the previous
> control register, and contains a bitmask to indicate the presence of each
> memory bank. This bitmask aligns with the previous control register
> bitmask that served the same purpose. The control and capability
> registers are treated like a C Union structure in order to support both
> the new and old revisions of the EMIF device.
> 
> Signed-off-by: Debarati Biswas <debaratix.biswas@intel.com>
> Signed-off-by: Russ Weight <russell.h.weight@intel.com>
> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
> ---

Thanks for the patch and for the review.

It is too late in the cycle for me to pick it up. I will take it after
the merge window.


Best regards,
Krzysztof