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From:   wangwudi <wangwudi@hisilicon.com>
To:     <linux-kernel@vger.kernel.org>
CC:     wangwudi <wangwudi@hisilicon.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>
Subject: [PATCH] drivers: irqchip: Allocate alignment addr by ITS_BASER.Page_size
Date:   Sat, 16 Jul 2022 15:05:36 +0800
Message-ID: <1657955136-6622-1-git-send-email-wangwudi@hisilicon.com>
MIME-Version: 1.0
Content-Type: text/plain
Precedence: bulk

The description of the ITS_BASER.Physical_Address field in the ARM GIC spec is as 
follows:
"The address must be aligned to the size specified in the Page Size field."
The Page_Size field in ITS_BASER might be RO.

Currently, the address is aligned based on the system page_size, not the HW 
Page_Size field. In some case, this is in contradiction with the spec.

For example:
ITS_BASER.Page_Size indicate 16K, and kernel page size is 4K.
If HW need 4K-size memory, the driver may alloc a 4K aligned address.
This has been proven in hardware.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Marc Zyngier <maz@kernel.org>
Signed-off-by: wangwudi <wangwudi@hisilicon.com>
---
 drivers/irqchip/irq-gic-v3-its.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 5ff09de6c48f..0e25e887d45c 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2310,6 +2310,9 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
 		order = get_order(GITS_BASER_PAGES_MAX * psz);
 	}
 
+	if ((psz > PAGE_SIZE) && (PAGE_ORDER_TO_SIZE(order) < psz)) {
+		order = get_order(psz);
+	}
 	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
 	if (!page)
 		return -ENOMEM;
-- 
2.7.4