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[2620:137:e000::1:20]) by mx.google.com with ESMTP id dm3-20020a05640222c300b0043acbf73479si12819596edb.458.2022.07.18.12.02.06; Mon, 18 Jul 2022 12:02:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=google header.b=d6GcSCh+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233607AbiGRS4U (ORCPT + 99 others); Mon, 18 Jul 2022 14:56:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233368AbiGRS4R (ORCPT ); Mon, 18 Jul 2022 14:56:17 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7DAD2F386 for ; Mon, 18 Jul 2022 11:56:16 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id z23so22994426eju.8 for ; Mon, 18 Jul 2022 11:56:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=OlTtr5Gd284OqEXfbDoqgh6rP1VAtWxhRShnoixkRbw=; b=d6GcSCh+7n/GZEZUJUNlmqvQFKgvgxpaE9K32+dORzvBulfX/UjyU2DOdjn25pdojM 7A/9kJsuMYbuoQEmbPXengBpsifDZ3oXqMqQJ4KMdfc6BxIMKG3O8vgbRnQcW9GlMAgS hLY0zHaAcbH7aXwIcfvl4n3qOFid9OPO5B+2w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OlTtr5Gd284OqEXfbDoqgh6rP1VAtWxhRShnoixkRbw=; b=iQHV+V5nt78dkMJtk5aviauTzoYdWmjlkzcXETprNSuwHRhoRA5LdS4dDlHftPWtVS TOEgJ7uTNWkSK2BAvqbQ0evF6paxKv2UYQp7y7CSCpwn/C8vZ9AJWmNnRhXxUaByJ2X5 e1IANitleCyN8c6HXYs9OJZSGzq/Q46LAR2pg3TPDrSxVoqEfQZwspf4ue9KgqxP4IL/ FlElDQRa/yNvZoVdYilWW7m3FaCGgPGBwAP7vhwJUd2ePdg/rf2/kWB5xPYBB9lllAib dAILdh7GJQvRV+uXrwYNw7pMZRnbUKTWujpDKae43gwIzl5XEGzPNy4/l5UgbhJZYnsU zVNA== X-Gm-Message-State: AJIora9axdekCUIRBUdZnCjq/DlFVJgu8HTAge01qysl5olAqJd+XvAf giNrWjB6jX6tKYkA90d30JCx8+9RrjwUoo2BTlegBw== X-Received: by 2002:a17:907:9809:b0:72f:817:d433 with SMTP id ji9-20020a170907980900b0072f0817d433mr14173469ejc.483.1658170575172; Mon, 18 Jul 2022 11:56:15 -0700 (PDT) MIME-Version: 1.0 References: <20220716222454.29914-3-jim2101024@gmail.com> <20220718181425.GA1431580@bhelgaas> In-Reply-To: <20220718181425.GA1431580@bhelgaas> From: Jim Quinlan Date: Mon, 18 Jul 2022 14:56:03 -0400 Message-ID: Subject: Re: [PATCH v2 2/6] PCI: brcmstb: Split brcm_pcie_setup() into two funcs To: Bjorn Helgaas Cc: Jim Quinlan , "open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" , Florian Fainelli , Lorenzo Pieralisi , Rob Herring , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="0000000000001ff22505e418ecbd" X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --0000000000001ff22505e418ecbd Content-Type: text/plain; charset="UTF-8" On Mon, Jul 18, 2022 at 2:14 PM Bjorn Helgaas wrote: > > On Sat, Jul 16, 2022 at 06:24:49PM -0400, Jim Quinlan wrote: > > Currently, the function does the setup for establishing PCIe link-up > > with the downstream device, and it does the actual link-up as well. > > The calling sequence is (roughly) the following in the probe: > > > > -> brcm_pcie_probe() > > -> brcm_pcie_setup(); /* Set-up and link-up */ > > -> pci_host_probe(bridge); > > > > This commit splits the setup function in two: brcm_pcie_setup(), which only > > does the set-up, and brcm_pcie_start_link(), which only does the link-up. > > The reason why we are doing this is to lay a foundation for subsequent > > commits so that we can turn on any power regulators, as described in the > > root port's DT node, prior to doing link-up. > > All drivers that care about power regulators turn them on before > link-up, but typically those regulators are described directly under > the host bridge itself. Hi Bjorn, Actually, what you describe is what I proposed with my v1 back in Nov 2020. The binding commit message said, "Quite similar to the regulator bindings found in "rockchip-pcie-host.txt", this allows optional regulators to be attached and controlled by the PCIe RC driver." > > IIUC the difference here is that you have regulators described under > Root Ports (not the host bridge/Root Complex itself), so you don't > know about them until you've enumerated the Root Ports. > brcm_pcie_probe() can't turn them on directly because it doesn't know > what Root Ports are present and doesn't know about regulators below > them. The reviewer's requested me to move the regulator node(s) elsewhere, and at some point later it was requested to be placed under the Root Port driver. I would love to return them under the host bridge, just say the word! > > So I think brcm_pcie_setup() does initialization that doesn't depend > on the link or any downstream devices, and brcm_pcie_start_link() does > things that depend on the link being up. Right? Yes. > > If so, "start_link" might be a slight misnomer since AFAICT > brcm_pcie_start_link() doesn't do anything to initiate link-up except > maybe deasserting fundamental reset. Some drivers start the LTSSM or > explicitly enable link training, but brcm_pcie_start_link() doesn't > seem to do anything like that. > > brcm_pcie_start_link() still does brcm_pcie_set_outbound_win(). Does > that really depend on the link being up? If that only affects the > Root Port, maybe it could be done before link-up? Some of the registers cannot be accessed until after linkup but these do not have that issue. I will change this. Jim Quinlan Broadcom STB > > > We do this by defining an > > add_bus() callback which is invoked during enumeraion. At the end of this > > patchset the probe function trace will look something like this: > > > > -> brcm_pcie_probe() > > -> brcm_pcie_setup(); /* Set-up only */ > > -> pci_host_probe(bridge); > > -> [enumeration] > > -> pci_alloc_child_bus() > > -> bus->ops->add_bus(bus); /* We've set this op */ > > -> brcm_pcie_add_bus() /* Our callback */ > > -> [turn on regulators] /* Main objective! */ > > -> brcm_pcie_start_link() /* Link-up */ --0000000000001ff22505e418ecbd Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smime.p7s" Content-Description: S/MIME Cryptographic Signature MIIQbgYJKoZIhvcNAQcCoIIQXzCCEFsCAQExDzANBglghkgBZQMEAgEFADALBgkqhkiG9w0BBwGg gg3FMIIFDTCCA/WgAwIBAgIQeEqpED+lv77edQixNJMdADANBgkqhkiG9w0BAQsFADBMMSAwHgYD VQQLExdHbG9iYWxTaWduIFJvb3QgQ0EgLSBSMzETMBEGA1UEChMKR2xvYmFsU2lnbjETMBEGA1UE AxMKR2xvYmFsU2lnbjAeFw0yMDA5MTYwMDAwMDBaFw0yODA5MTYwMDAwMDBaMFsxCzAJBgNVBAYT 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