Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Tue, 19 Jul 2022 08:45:44 +0800
From:   Huang Rui <ray.huang@amd.com>
To:     "Yuan, Perry" <Perry.Yuan@amd.com>
Cc:     "rafael.j.wysocki@intel.com" <rafael.j.wysocki@intel.com>,
        "viresh.kumar@linaro.org" <viresh.kumar@linaro.org>,
        "Sharma, Deepak" <Deepak.Sharma@amd.com>,
        "Limonciello, Mario" <Mario.Limonciello@amd.com>,
        "Fontenot, Nathan" <Nathan.Fontenot@amd.com>,
        "Deucher, Alexander" <Alexander.Deucher@amd.com>,
        "Su, Jinzhou (Joe)" <Jinzhou.Su@amd.com>,
        "Huang, Shimmer" <Shimmer.Huang@amd.com>,
        "Du, Xiaojian" <Xiaojian.Du@amd.com>,
        "Meng, Li (Jassmine)" <Li.Meng@amd.com>,
        "linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 02/13] cpufreq: amd-pstate: enable AMD Precision Boost
 mode switch
Message-ID: <YtX+uF/nAIG0ykHN@amd.com>
References: <cover.1657876961.git.Perry.Yuan@amd.com>
 <b3db7981e407d5f111eeb27a8504a4ed7979ba60.1657876961.git.Perry.Yuan@amd.com>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <b3db7981e407d5f111eeb27a8504a4ed7979ba60.1657876961.git.Perry.Yuan@amd.com>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?ZXBU+oE3MU9IKjAhu9nZTTgK4tWKEk6gba9KSZzgDoZXmzQSEx/KB9xV+QIJ?=
 =?us-ascii?Q?yUjQyogOLom6ehBVirqOo3uvh+XkQ8sKc4Yd3DCyLuH/Xv1PV3pdISX2gTH6?=
 =?us-ascii?Q?UOL+nY9/A1YNohynUhb4K1i7MIdDPf3PB2axfNv5dfWuMEn17AJ9Om64LPI3?=
 =?us-ascii?Q?ZZxKPpbGXwcN+el4x4Wm88sKqGR3+yeRtacQz/zw0b2y10CnCm0eARGw8/8o?=
 =?us-ascii?Q?AmSKYzwIIEdJj8LGk481aElOsIaOvbaFb5v+6ktbHTSGoXo+/8DwlxxNWvTR?=
 =?us-ascii?Q?tzlW1aJ6x5Ys9EyixZxGmsHjB0qGChp1ytXuMm82zTL5vBHsr+pMCx5Vi5iU?=
 =?us-ascii?Q?4+1FBpb2J2RR+7usqogo5Rwut+qBND3WbPcozZvGAyApme5yrmIC8ZQCZcOJ?=
 =?us-ascii?Q?OeO7JZF01hO8eCei4aQpd9IrDpcctOxFaWAC7vi9S4Yr9Zak9/Xu1tKnx5NO?=
 =?us-ascii?Q?XOKoiMmUz4DnHwPDTcaNT+jOwMqmsZMXCCW6WhtGFZP4NjR7xGIAgOLf1ppq?=
 =?us-ascii?Q?yeKPbGGZj8K52Q8XUJuY2krfz7RMuVucy+VpF2I7AewnsDIqN+gbDJXKe4cM?=
 =?us-ascii?Q?hYg425xOtLC8xTkzrNVLeEOL3aERBtfVgX4EyoPGJzr3v636TyM5qBykC/dU?=
 =?us-ascii?Q?r/jsoGS8gyujpaL+KXNKKGbt6QrJha29WkdKGnUwJLyVMvWvLmlqZ4aOx9qV?=
 =?us-ascii?Q?G9CEUQQaNRxCZBYh7N3qeX0z/WZrQAk/1JTCCooMsoj1+3ZhDJCMpF6psdGe?=
 =?us-ascii?Q?Ht4l+Cp9fS/6zYAqLTsSLC/uf1oiigIovkVN0NFSIsgQ80ySgQx98eCsOVx9?=
 =?us-ascii?Q?4nRJFLoxn7fiOzzOQV+e7LQlwlVLR2m9eIYVM51zgPaTfcFOiqCY25TT2v1S?=
 =?us-ascii?Q?Fv15jX2l24Wb4KXRm/rA5YMO4p12zPiUXe/DVry5ujFTK2+e8DfFZBt44dzB?=
 =?us-ascii?Q?2XNdTAnmQhBXygecSRUKEYoVEDyxODVzyKUo/3aE/iYv2j5cn29Dm4k8WOAz?=
 =?us-ascii?Q?1VNGVzR/kPSKXfzQiUiw6TYSGhzLCRgzTsLfDvxBBKBg7DMGyxXCSXPBPuX+?=
 =?us-ascii?Q?nNNUT5iyBU0swmRhDioQa7XaaScidJ/plF8ngZrfi0nZUMvCem4TVquiPVtD?=
 =?us-ascii?Q?ISGwUFnt6fl+GnY0lrx4vqp05KYcCfpxmD/M3rg/obs4mWXKPC7odIVJx9HN?=
 =?us-ascii?Q?Oi+IXMZFwXp4g/8GJYLGykmQ1HYpNINZZqxwOQ/RHipkQbCua8XnoL8DhRQY?=
 =?us-ascii?Q?GM8lePSyM5ENsCwcI1rvthusQFZtJNHC7FwMMufcwiWQg71YYxGPvGohTLhL?=
 =?us-ascii?Q?I97HnkShRnAJ/hBRpCzUlf3AZ0a1Fd9Bc6n8RyH8gPugTyBFsyvDko1Hz2+0?=
 =?us-ascii?Q?8MSGpteVntXGiBl7Tw7lFl8xhJ26qV/QKHQTjB0PW8T88hjc38jZTJAWitDy?=
 =?us-ascii?Q?aVawimnDgtDkz5vQLRyEHUS/o11Xq5TC7qno+jO//btIhysd8fAPyn/p9jlF?=
 =?us-ascii?Q?cbsBF/Igad9Mv94VZQDQ1q3rV+seXTYf6QjsxxdohEUlJIkq1kcIG/sg8Zu0?=
 =?us-ascii?Q?VBUzUppGthAAhI1ooYJdSUaE4O3PUibHTbG9qV9A?=
X-OriginatorOrg: amd.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 859e7755-6b54-4386-e200-08da692010f2
X-MS-Exchange-CrossTenant-AuthSource: DM5PR12MB2504.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2022 00:46:07.4319
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: v7X+jdq13013/Gj+tMHi/MF4uteiZyi2qRTUkZ4qWlQdIgjPh9swVg4pN1J9co6UkLUhG3Esx7IixwN7mRxEbw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4826
X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,
        RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham
        autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Fri, Jul 15, 2022 at 06:04:21PM +0800, Yuan, Perry wrote:
> Add support to switch AMD precision boost state to scale cpu max
> frequency that will help to improve the processor throughput.
> 
> when set boost state to be enabled, user will need to execute below commands,
> the CPU will reach absolute maximum performance level or the highest perf which
> CPU physical support. This performance level may not be sustainable for
> long durations, it will help to improve the IO workload tasks.
> 
> * turn on CPU boost state under root
>   echo 1 > /sys/devices/system/cpu/cpufreq/boost
> 
> If user set boost off,the CPU can reach to the maximum sustained
> performance level of the process, that level is the process can maintain
> continously working and definitely it can save some power compared to
> boost on mode.
> 
> * turn off CPU boost state under root
>   echo 0 > /sys/devices/system/cpu/cpufreq/boost
> 
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> ---
>  arch/x86/include/asm/msr-index.h |  2 ++
>  drivers/cpufreq/amd-pstate.c     | 22 +++++++++++++++++++---
>  2 files changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 869508de8269..b952fd6d6916 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -559,6 +559,8 @@
>  #define AMD_CPPC_MIN_PERF(x)		(((x) & 0xff) << 8)
>  #define AMD_CPPC_DES_PERF(x)		(((x) & 0xff) << 16)
>  #define AMD_CPPC_ENERGY_PERF_PREF(x)	(((x) & 0xff) << 24)
> +#define AMD_CPPC_PRECISION_BOOST_BIT	25
> +#define AMD_CPPC_PRECISION_BOOST_ENABLED	BIT_ULL(AMD_CPPC_PRECISION_BOOST_BIT)

The bit 25 (CpbDis) of MSRC001_0015 [Hardware Configuration] indicates the
core performance boost disable flag.

Please see the section 17.2 Core Performance Boost of PPR:

https://www.amd.com/system/files/TechDocs/40332.pdf

Core performance boost (CPB) dynamically monitors processor activity to
create an estimate of power consumption. If the estimated processor
consumption is below an internally defined power limit and software has
requested P0 on a given core, hardware may transition the core to a
frequency and voltage beyond those defined for P0. If the estimated power
consumption exceeds the defined power limit, some or all cores are limited
to the frequency and voltage defined by P0.

The boost state is designed for legacy ACPI P-State function which is
to request higher frequency beyond P0 State (it's equal to nominal
frequency in CPPC), and we already have the operation like
MSR_K7_HWCR_CPB_DIS in acpi-cpufreq driver. However, in CPPC, we can modify
the performance hint beyond the nominal perf to reach the goal. That won't
need this control anymore. And furthermore, this function for legacy ACPI
P-State should not be mixed them up with CPPC policy. We should prevent the
effect for this flag in CPPC.

Thanks,
Ray

>  
>  /* AMD Performance Counter Global Status and Control MSRs */
>  #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS	0xc0000300
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 9ac75c1cde9c..188e055e24a2 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -122,6 +122,7 @@ struct amd_cpudata {
>  
>  	u64 freq;
>  	bool	boost_supported;
> +	u64 	cppc_hw_conf_cached;
>  };
>  
>  static inline int pstate_enable(bool enable)
> @@ -438,18 +439,27 @@ static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state)
>  {
>  	struct amd_cpudata *cpudata = policy->driver_data;
>  	int ret;
> +	u64 value;
>  
>  	if (!cpudata->boost_supported) {
>  		pr_err("Boost mode is not supported by this processor or SBIOS\n");
>  		return -EINVAL;
>  	}
>  
> -	if (state)
> +	ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_HW_CTL, &value);
> +	if (ret)
> +		return ret;
> +
> +	if (state) {
> +		value |= AMD_CPPC_PRECISION_BOOST_ENABLED;
>  		policy->cpuinfo.max_freq = cpudata->max_freq;
> -	else
> +	} else {
> +		value &= ~AMD_CPPC_PRECISION_BOOST_ENABLED;
>  		policy->cpuinfo.max_freq = cpudata->nominal_freq;
> -
> +	}
>  	policy->max = policy->cpuinfo.max_freq;
> +	WRITE_ONCE(cpudata->cppc_hw_conf_cached, value);
> +	wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_HW_CTL, value);
>  
>  	ret = freq_qos_update_request(&cpudata->req[1],
>  				      policy->cpuinfo.max_freq);
> @@ -478,6 +488,7 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
>  	int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;
>  	struct device *dev;
>  	struct amd_cpudata *cpudata;
> +	u64 value;
>  
>  	dev = get_cpu_device(policy->cpu);
>  	if (!dev)
> @@ -542,6 +553,11 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
>  
>  	policy->driver_data = cpudata;
>  
> +	ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_HW_CTL, &value);
> +	if (ret)
> +		return ret;
> +	WRITE_ONCE(cpudata->cppc_hw_conf_cached, value);
> +
>  	amd_pstate_boost_init(cpudata);
>  
>  	return 0;
> -- 
> 2.32.0
>