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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB5278.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 864ce7db-6bf1-4275-d70a-08da69508fad X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Jul 2022 06:33:15.4556 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hSaMF/FF6vDcoboOz+GJWFd0bBngwKi/h8bvAuJaYh8qgwHrvGC5I2yUrv/ZnJL0RuluMC5Cy5NAVDqbYJNqXw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6359 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org [AMD Official Use Only - General] Hi Ray.=20 > -----Original Message----- > From: Huang, Ray > Sent: Tuesday, July 19, 2022 9:05 AM > To: Yuan, Perry > Cc: rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; Sharma, Deepak > ; Limonciello, Mario > ; Fontenot, Nathan > ; Deucher, Alexander > ; Su, Jinzhou (Joe) ; > Huang, Shimmer ; Du, Xiaojian > ; Meng, Li (Jassmine) ; linux- > pm@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v4 11/13] cpufreq: amd_pstate: update transition dela= y > time to 1ms >=20 > On Fri, Jul 15, 2022 at 06:04:30PM +0800, Yuan, Perry wrote: > > Update transition delay time to 1ms, in the AMD CPU autonomous mode > > and non-autonomous mode, CPPC firmware will decide frequency at 1ms > > timescale based on the workload utilization. > > > > Acked-by: Viresh Kumar > > Signed-off-by: Perry Yuan > > Signed-off-by: Su Jinzhou >=20 > Please squeeze this patch into patch 9. I don't really want to separate t= he > transition marco update as two patches. >=20 > Thanks, > Ray Will update this in V5. Thanks. Perry. >=20 > > --- > > drivers/cpufreq/amd-pstate.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/cpufreq/amd-pstate.c > > b/drivers/cpufreq/amd-pstate.c index 4f8600a36194..d3bc441b3923 100644 > > --- a/drivers/cpufreq/amd-pstate.c > > +++ b/drivers/cpufreq/amd-pstate.c > > @@ -42,7 +42,7 @@ > > #include "amd-pstate-trace.h" > > > > #define AMD_PSTATE_TRANSITION_LATENCY 20000 > > -#define AMD_PSTATE_TRANSITION_DELAY 500 > > +#define AMD_PSTATE_TRANSITION_DELAY 1000 > > > > /* > > * TODO: We need more time to fine tune processors with shared memory > > solution > > -- > > 2.32.0 > >