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From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To:     Santosh Shilimkar <ssantosh@kernel.org>, tianfei.zhang@intel.com
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        trix@redhat.com, russell.h.weight@intel.com,
        linux-fpga@vger.kernel.org, debaratix.biswas@intel.com,
        matthew.gerlach@linux.intel.com, yilun.xu@intel.com,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] memory: dfl-emif: Update the dfl emif driver support revision 1
Date:   Tue, 19 Jul 2022 10:33:41 +0200
Message-Id: <165821962017.31298.6008809074231024823.b4-ty@linaro.org>
In-Reply-To: <20220713130355.196115-1-tianfei.zhang@intel.com>
References: <20220713130355.196115-1-tianfei.zhang@intel.com>
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On Wed, 13 Jul 2022 09:03:55 -0400, Tianfei Zhang wrote:
> From: Debarati Biswas <debaratix.biswas@intel.com>
> 
> The next generation (revision 1) of the DFL EMIF feature device requires
> support for more than 4 memory banks. It does not support the selective
> clearing of memory banks. A capability register replaces the previous
> control register, and contains a bitmask to indicate the presence of each
> memory bank. This bitmask aligns with the previous control register
> bitmask that served the same purpose. The control and capability
> registers are treated like a C Union structure in order to support both
> the new and old revisions of the EMIF device.
> 
> [...]

Applied, thanks!

[1/1] memory: dfl-emif: Update the dfl emif driver support revision 1
      https://git.kernel.org/krzk/linux-mem-ctrl/c/d16232de82d64ce02fe6d43aa51de004755de5e5

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>