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Date:   Tue, 19 Jul 2022 01:54:17 -0700
From:   Wojciech Bartczak <wbartczak@marvell.com>
To:     Pali =?iso-8859-1?Q?Roh=E1r?= <pali@kernel.org>
CC:     <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>
Subject: Re: Issues with A3720 PCIe controller driver pci-aardvark.c
Message-ID: <20220719085417.GA25397@proliant-dl360>
References: <20210723221710.wtztsrddudnxeoj3@pali>
 <20220216200940.fwdwk5rcb4zq6dyg@pali> <20220710112108.jegpz4khfsrb4ahd@pali>
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On Sun, Jul 10, 2022 at 01:21:08PM +0200, Pali Roh?r wrote:
> + Other people from Marvell active on LKML.
> 
> Could you please look at this issue and give us some comment? It is
> really critical issue which needs to be solved.
> 

Hi Pali,

Thank you for reaching me out. I hope I can help.
I don't work directly over Armada A3720 nor knowing anyone from team.
Unfortunately, this means I have no access to the data/code you are
looking for. Nevertheless, I have escalated this problem internally.
I believe this should help to get to right people which can investigate
patch/issue and do actual work.

Kind regards,
Wojciech.

> On Wednesday 16 February 2022 21:09:40 Pali Roh?r wrote:
> > + Bharat, Veerasenareddy and Wojciech from Marvell
> > 
> > Hello! Could you please look at this email and help us with this Marvell HW issue?
> > 
> > On Saturday 24 July 2021 00:17:10 Pali Roh?r wrote:
> > > Hello Konstantin!
> > > 
> > > There are issues with Marvell Armada 3720 PCIe controller when high
> > > performance PCIe card (e.g. WiFi AX) is connected to this SOC. Under
> > > heavy load PCIe controller sends fatal abort to CPU and kernel crash.
> > > 
> > > In Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions
> > > document is described erratum 3.12 PCIe Completion Timeout (Ref #: 251)
> > > which may be relevant. But neither Bjorn, Thomas nor me were able to
> > > understood text of this erratum. And we have already spent lot of time
> > > on this erratum. My guess that is that in erratum itself are mistakes
> > > and there are missing some other important details.
> > > 
> > > Konstantin, are you able to understand this erratum? Or do you know
> > > somebody in Marvell who understand this erratum and can explain details
> > > to us? Or do you know some more details about this erratum?
> > > 
> > > Also it would be useful if you / Marvell could share text of this
> > > erratum with linux-pci people as currently it is available only on
> > > Marvell Customer Portal which requires registration with signed NDA.
> > > 
> > > In past Thomas wrote patch "according to this erratum" and I have
> > > rebased, rewritten and resent it to linux-pci mailing list for review:
> > > https://lore.kernel.org/linux-pci/20210624222621.4776-6-pali@kernel.org/
> > > 
> > > Similar patch is available also in kernel which is part of Marvell SDK.
> > > 
> > > Bjorn has objections for this patch as he thinks that bit DIS_ORD_CHK in
> > > that patch should be disabled. Seems that enabling this bit effectively
> > > disables PCIe strong ordering model. PCIe kernel drivers rely on PCIe
> > > strong ordering, so it would implicate that that bit should not be
> > > enabled. Which is opposite of what is mentioned patch doing.
> > > 
> > > Konstantin, could you help us with this problem?