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[209.85.219.174]) by smtp.gmail.com with ESMTPSA id bq6-20020a05620a468600b006b5fbc3035bsm2336467qkb.117.2022.07.19.07.22.20 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Jul 2022 07:22:21 -0700 (PDT) Received: by mail-yb1-f174.google.com with SMTP id 75so26720999ybf.4 for ; Tue, 19 Jul 2022 07:22:20 -0700 (PDT) X-Received: by 2002:a5b:6c1:0:b0:669:a7c3:4c33 with SMTP id r1-20020a5b06c1000000b00669a7c34c33mr30846962ybq.543.1658240540695; Tue, 19 Jul 2022 07:22:20 -0700 (PDT) MIME-Version: 1.0 References: <20220704101605.1318280-1-sudeep.holla@arm.com> <20220704101605.1318280-10-sudeep.holla@arm.com> In-Reply-To: <20220704101605.1318280-10-sudeep.holla@arm.com> From: Geert Uytterhoeven Date: Tue, 19 Jul 2022 16:22:09 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v6 09/21] arch_topology: Add support to parse and detect cache attributes To: Sudeep Holla Cc: Linux Kernel Mailing List , Greg Kroah-Hartman , Conor Dooley , valentina.fernandezalanis@microchip.com, Vincent Guittot , Dietmar Eggemann , Qing Wang , Rob Herring , "Rafael J . Wysocki" , Ionela Voinescu , Pierre Gondois , Linux ARM , linux-riscv , Gavin Shan Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Sudeep, On Mon, Jul 4, 2022 at 12:19 PM Sudeep Holla wrote: > Currently ACPI populates just the minimum information about the last > level cache from PPTT in order to feed the same to build sched_domains. > Similar support for DT platforms is not present. > > In order to enable the same, the entire cache hierarchy information can > be built as part of CPU topoplogy parsing both on ACPI and DT platforms. > > Note that this change builds the cacheinfo early even on ACPI systems, > but the current mechanism of building llc_sibling mask remains unchanged. > > Tested-by: Ionela Voinescu > Reviewed-by: Gavin Shan > Signed-off-by: Sudeep Holla Thanks for your patch! > --- a/drivers/base/arch_topology.c > +++ b/drivers/base/arch_topology.c > @@ -7,6 +7,7 @@ > */ > > #include > +#include > #include > #include > #include > @@ -780,15 +781,28 @@ __weak int __init parse_acpi_topology(void) > #if defined(CONFIG_ARM64) || defined(CONFIG_RISCV) > void __init init_cpu_topology(void) > { > + int ret, cpu; > + > reset_cpu_topology(); > + ret = parse_acpi_topology(); > + if (!ret) > + ret = of_have_populated_dt() && parse_dt_topology(); > > - /* > - * Discard anything that was parsed if we hit an error so we > - * don't use partial information. > - */ > - if (parse_acpi_topology()) > - reset_cpu_topology(); > - else if (of_have_populated_dt() && parse_dt_topology()) > + if (ret) { > + /* > + * Discard anything that was parsed if we hit an error so we > + * don't use partial information. > + */ > reset_cpu_topology(); > + return; > + } > + > + for_each_possible_cpu(cpu) { > + ret = detect_cache_attributes(cpu); > + if (ret) { > + pr_info("Early cacheinfo failed, ret = %d\n", ret); This is triggered Early cacheinfo failed, ret = -12 on all my RV64 platforms (K210, PolarFire, StarLight). -12 = -ENOMEM. The boot continues regardless, and the K210 even has enough spare RAM after boot to run "ls", unlike two weeks ago ;-) > + break; > + } > + } > } Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds