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From:   "Mahapatra, Amit Kumar" <amit.kumar-mahapatra@amd.com>
To:     Mark Brown <broonie@kernel.org>
CC:     Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>,
        "p.yadav@ti.com" <p.yadav@ti.com>,
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Subject: RE: [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI
 device
Thread-Topic: [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI
 device
Thread-Index: AQHYeZhXApErq+32kkmuJFVVfXogSAG7F8aMAeAoVR+snXQgIICishAAgCJ4JhCAAFqwgIAF7C1A
Date:   Tue, 19 Jul 2022 13:21:41 +0000
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Hello Mark,

> -----Original Message-----
> From: Mark Brown <broonie@kernel.org>
> Sent: Friday, July 15, 2022 9:24 PM
> To: Mahapatra, Amit Kumar <amit.kumar-mahapatra@amd.com>
> Cc: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>;
> p.yadav@ti.com; miquel.raynal@bootlin.com; richard@nod.at;
> vigneshr@ti.com; git@xilinx.com; michal.simek@xilinx.com; linux-
> spi@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; michael@walle.cc; linux-mtd@lists.infradead.org;
> git (AMD-Xilinx) <git@amd.com>
> Subject: Re: [RFC PATCH 1/2] spi: Add multiple CS support for a single SP=
I
> device
>=20
> On Fri, Jul 15, 2022 at 03:35:49PM +0000, Mahapatra, Amit Kumar wrote:
>=20
> > > That doesn't address the issue, the issue is checking that the
> > > driver can support multiple chip selects.
>=20
> > To address this issue, in spi core we will check the number of items
> > in the "reg" property of the flash node(which is nothing but the
> > number of chip selects) against the "num-cs" property of the spi
> > controller(which is total number of chip selects supported by the
> > controller). If the number of items mentioned in the "reg" property is
> > greater than "num-cs" value then we error out.
>=20
> > For eg.,
>=20
> > rc =3D of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
> > 						SPI_CS_CNT_MAX);
> > if(rc > ctlr->num_chipselect) {
> > 	dev_err(&ctlr->dev, "%pOF has invalid 'reg' property (%d)\n",
> > 							nc, rc);
> > 	return -EINVAL;
> > }
>=20
> This would check that the controller has at least the number of chip sele=
cts
> specified but it would not check that the controller is actually capable =
of
> using more than one chip select at once. We should be validating both tha=
t

I agree, so for checking the controller multiple chip select capability(usi=
ng=20
more than one chip select at once) we can define a new spi controller DT=20
property like "multi-cs-cap"(please suggest a better name).=20
The controller that can support multiple chip selects should have this prop=
erty=20
in the spi controller DT node. The spi core will check ctlr->multi-cs-cap t=
o=20
operate multiple chip select in parallel.

> the chip selects are available and that the controller can do something u=
seful
> with them (and probably have an implementation in the core for doing so v=
ia
> GPIO).

Here are you referring to the usecase in which a controller implementing mu=
lti CS
support using GPIO? =20


Regards,
Amit