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[2620:137:e000::1:20]) by mx.google.com with ESMTP id w2-20020a056808018200b0033a79c03129si5382790oic.145.2022.07.19.08.34.53; Tue, 19 Jul 2022 08:35:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=ovGLk68q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237923AbiGSPby (ORCPT + 99 others); Tue, 19 Jul 2022 11:31:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237369AbiGSPbp (ORCPT ); Tue, 19 Jul 2022 11:31:45 -0400 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F390C5887C; Tue, 19 Jul 2022 08:31:44 -0700 (PDT) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 26JD8AR7030475; Tue, 19 Jul 2022 17:31:26 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=selector1; bh=1ralePF7NZgiuaaEZtba9R7/B4WF8Zv4f9q+QOtg1so=; b=ovGLk68qwlCYzXBtDnHzdBiVd7/Agced4hab8SCCtj6Q2qS3vg2skCuapG+9vWhaXcw+ wCgLgNAQsqMJJN1uOuiwF1smm59WOeRSbI1wl3um/QUEFSeAhzqVGzK0YWdmUOyNTFkc Ka1PUJqGEGmsPXn1YLUPCvbXAOuRe30vXl2PlYrQpjdbA7jyGjQ6VOEVACI8Tf0OSOUV +pkTQS1qpenJFg9/Y0gcFAG1oGgXhB5eibtNEoOqepyu596lqTqk2y1VuSwep3lNpPFh rkcPqeJ0p4lzAL+L99UKTSKLdxBTGTphF4TMnVyTzU1MCcwktEjMkJAubfAhvUryWb8A xQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3hdrwwjf19-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Jul 2022 17:31:26 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CFD6A10002A; Tue, 19 Jul 2022 17:31:25 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CAE7B22AFE6; Tue, 19 Jul 2022 17:31:25 +0200 (CEST) Received: from localhost (10.75.127.44) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.20; Tue, 19 Jul 2022 17:31:24 +0200 From: Amelie Delaunay To: Jonathan Corbet , Vinod Koul , Maxime Coquelin , Alexandre Torgue CC: , , , , , Marek Vasut , Amelie Delaunay Subject: [PATCH v3 0/6] STM32 DMA-MDMA chaining feature Date: Tue, 19 Jul 2022 17:31:16 +0200 Message-ID: <20220719153122.620730-1-amelie.delaunay@foss.st.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-19_04,2022-07-19_01,2022-06-22_01 X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patchset (re)introduces STM32 DMA-MDMA chaining feature. As the DMA is not able to generate convenient burst transfer on the DDR, it penalises the AXI bus when accessing the DDR. While it accesses optimally the SRAM. The DMA-MDMA chaining then consists in having an SRAM buffer between DMA and MDMA, so the DMA deals with peripheral and SRAM, and the MDMA with SRAM and DDR. The feature relies on the fact that DMA channel Transfer Complete signal can trigger a MDMA channel transfer and MDMA can clear the DMA request by writing to DMA Interrupt Clear register. A deeper introduction can be found in patch 1. Previous implementation [1] has been dropped as nacked. Unlike this previous implementation (where all the stuff was embedded in stm32-dma driver), the user (in peripheral drivers using dma) has now to configure the MDMA channel. [1] https://lore.kernel.org/lkml/1538139715-24406-1-git-send-email-pierre-yves.mordret@st.com/ Changes in v3: - introduce two prior patches to help readibility - fix stm32-dma struct stm32_dma_mdma_config documentation Changes in v2: - wrap to 80-column limit for documentation - add an entry for this documentation in index.rst - use simple table instead of csv-table in documentation Amelie Delaunay (6): dmaengine: stm32-dma: introduce 3 helpers to address channel flags dmaengine: stm32-dma: use bitfield helpers docs: arm: stm32: introduce STM32 DMA-MDMA chaining feature dmaengine: stm32-dmamux: set dmamux channel id in dma features bitfield dmaengine: stm32-dma: add support to trigger STM32 MDMA dmaengine: stm32-mdma: add support to be triggered by STM32 DMA Documentation/arm/index.rst | 1 + .../arm/stm32/stm32-dma-mdma-chaining.rst | 415 ++++++++++++++++++ drivers/dma/stm32-dma.c | 136 +++--- drivers/dma/stm32-dmamux.c | 2 +- drivers/dma/stm32-mdma.c | 70 ++- 5 files changed, 569 insertions(+), 55 deletions(-) create mode 100644 Documentation/arm/stm32/stm32-dma-mdma-chaining.rst -- 2.25.1